High density flash memory

• US 5,936,274 A
• Filed: 07/08/1997
• Issued: 08/10/1999
• Est. Priority Date: 07/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US08/889,553
• Time in Patent Office: 763 Days
• Field of Search: 257/314, 257/315, 257/316, 257/321, 438/259
• US Class Current: 257/315
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar. The control gates are formed together with interconnecting gate lines. First source/drain terminals are row addressable by interconnection lines disposed substantially orthogonal to the gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only 2F² is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than 2F² is needed per bit of data.

Claims

1. A memory cell, comprising:

a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source/drain and body regions wherein the source/drain regions are formed within the pillar, the pillar having a number of sides;

a number of floating gates, each gate associated with only one side of the pillar; and

a number of control gates, each control gate associated with only one floating gate so as to allow selective storage and retrieval of data on the floating gates.

2. The memory cell of claim 1, wherein the control gate is capable of storing more than two charge states on its associated floating gate.

3. The memory cell of claim 1, wherein the substrate is a bulk semiconductor.

4. The memory cell of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor substrate.

5. A memory device, comprising:

an array of memory cells, each cell including at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that forms source/drain and body regions for the transistors within the pillar and at least a pair of floating gates disposed adjacent to the opposing sides of the pillar;

a plurality of gate lines that are substantially parallel, each gate line allowing selective storage and retrieval of data on ones of the floating gates;

at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

6. The memory device of claim 5, wherein the pillar extends outwardly from a bulk semiconductor substrate.

7. The memory device of claim 5, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.

8. A memory device, comprising:

an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions within the pillar for the transistors and a number of gates each disposed adjacent to only one of the sides of the pillar;

a plurality of gate lines, each gate line interconnecting ones of the gates in ones of the memory cells;

at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

9. The memory device of claim 8, wherein the pillar extends outwardly from a bulk semiconductor substrate.

10. The memory device of claim 8, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.

11. A floating gate transistor that is fabricated upon a substrate, the transistor comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric formed on at least a portion of one side surface of the pillar;

a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a control gate, substantially adjacent to the floating gate and insulated therefrom; and

an intergate dielectric, interposed between the floating and control gates.

12. The floating gate transistor of claim 11, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.

13. The floating gate transistor of claim 11, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

14. A memory cell that is fabricated upon a substrate, the memory cell comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric formed on at least a portion of only one side surface of the pillar;

a plurality of floating gates, each of which is substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a plurality of control gates, each of which is substantially adjacent to one of the floating gates and insulated therefrom; and

an intergate dielectric, interposed between each of the substantially adjacent floating and control gates.

15. The memory cell of claim 14, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.

16. The memory cell of claim 14, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

17. A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising:

a plurality of memory cells, each memory cell including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric, formed on at least a portion of only one side surface of the pillar;

a floating gate, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a control gate, substantially adjacent to the floating gate and insulated therefrom; and

an intergate dielectric, interposed between the floating gate and the control gate;

a plurality of gate lines interconnecting ones of the control gates in ones of the memory cells;

at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

18. The memory array of claim 17, wherein the substrate is a bulk semiconductor from which the pillar outwardly extends.

19. The memory array of claim 17, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

20. The memory array of claim 17, wherein the at least one first source/drain interconnection line is formed at least partially within the substrate.

21. The memory array of claim 17, wherein the gate lines are substantially parallel.