MOSFET for input/output protective circuit having a multi-layered contact structure with multiple contact holes on a single diffusion layer

• US 5,936,283 A
• Filed: 08/05/1997
• Issued: 08/10/1999
• Est. Priority Date: 08/05/1996
• Status: Expired due to Term

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Narita, Kaoru, Fujii, Takeo
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US08/906,336
• Time in Patent Office: 735 Days
• Field of Search: 257/324, 257/342, 257/343, 257/382-384, 257/459, 257/486, 257/271, 257/341, 257/355, 257/358, 257/359, 257/360, 257/363, 257/396, 257/503, 257/700, 257/748, 438/233, 438/622, 438/652
• US Class Current: 257/355
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to the present invention, a MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate comprises a high melting point metal silicide layer disposed on the drain diffusion layer through a first insulating film, a metal wire layer disposed on the high melting point metal silicide layer through a second insulating film, at least two first contact holes for electrically connecting the high melting point metal silicide layer and the metal wire layer, and a second contact hole for electrically connecting the high melting point metal silicide layer and the drain diffusion layer, wherein the second contact hole is disposed at a substantial center between the two first contact holes.

Claims

1. A MOSFET for an input/output protective circuit in which a diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate, said MOSFET further comprising:

a first insulating film with a first contact hole formed therein and formed on the substrate;

a second insulating layer with a second contact hole and a third contact hole formed therein and formed above said insulating film;

a high melting point metal silicide layer disposed on an upper surface of said first insulating film, said high melting point silicide layer being in electrical contact with said drain diffusion layer through the first contact hole formed in the first insulating film;

a metal wire layer disposed on said second insulating film, said metal wire layer being in electrical contact with said high melting point metal silicide layer which is formed on said upper surface of the first insulating film through the second and third contact holes formed in the second insulating film;

wherein said first contact hole formed in said first insulating film is disposed at a substantial center between said second and third contact holes formed in said second insulating film.

2. The MOSFET for an input/output protective circuit according to claim 1, wherein said metal wire layer is connected to an external terminal.

3. The MOSFET for an input/output protective circuit according to claim 1, wherein a high melting point metal and a barrier metal layer are embedded in said second and third contact holes to electrically connect the metal wire layer with said high melting point silicide layer and, a high melting point metal silicide is disposed in said first contact hole to electrically connect said high melting point silicide layer with said drain diffusion layer.

4. A MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate, comprising:

a first insulating film disposed on said drain diffusion layer;

a first contact hole, formed by one part of said first insulating film being removed, and thereby said drain diffusion layer being exposed;

a high melting point metal silicide layer disposed on said first insulating film, at a bottom and on a side of said first contact hole;

a second insulating film disposed on said high melting point metal silicide layer;

two second contact holes, formed by two parts of said second insulating film being removed, and thereby said high melting point metal silicide layer being exposed;

an embedded metal layer embedded in said two second contact holes; and

a metal wire layer disposed on said second insulating film and electrically connected to said embedded metal layer,

wherein two portions of said high melting point metal silicide layer are exposed from said two second contact holes, a length from one exposed portion to said high melting point metal silicide layer at the bottom of said first contact hole is substantially equal to that from the other exposed portion to said high melting point metal silicide layer at the bottom of said first contact hole.

5. The MOSFET for an input/output protective circuit according to claim 4, wherein said embedded metal layer includes a high melting point metal and a barrier metal layer.

6. A MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate, said MOSFET comprising:

a first insulating film disposed on said drain diffusion layer;

a plurality of first contact holes, formed by parts of said first insulating film being removed, and thereby said drain diffusion layer being exposed;

a continuous high melting point metal silicide layer disposed on an upper surface of said first insulating film, at the bottom and on the side of said plurality of first contact holes;

a second insulating film disposed on said high melting point metal silicide layer;

a plurality of second contact holes, formed by parts of said second insulating film being removed, and thereby said high melting point metal silicide layer being exposed

a plurality of embedded metal layers embedded in said plurality of second contact holes to be in electrical contact with said high melting point silicide layer; and

a metal wire layer disposed on said second insulating film and electrically connected to said plurality of embedded metal layers, said embedded metal layers providing electrical contact between said metal wire layer and said high melting point silicide layer,

wherein said plurality of first contact holes and said plurality of second contact hole are disposed so that they are alternately connected to said high metal point metal silicide layer, and respective distances between said first and second contact holes are substantially equal to one another.

7. A semiconductor device comprising:

a diffusion layer formed in a semiconductor substrate;

a first insulating film formed on said diffusion layer;

a plurality of first contact holes selectively formed in said first insulating film to expose a plurality of parts of said diffusion layer, respectively;

a first layer serving as a resistor and being disposed on an upper surface of said first insulating film in contact with the respective parts of said diffusion layer through said first contact holes;

a second insulating film formed on said first layer;

at least one second contact hole selectively formed in said second insulating film to expose at least one part of said first layer which is formed on the upper surface of said first insulating film; and

a conductive layer formed on said second insulating film in contact with said part of said first layer through said second contact hole.

8. The semiconductor device according to claim 7, wherein said second contact hole is positioned in plane view between adjacent ones of said first contact holes.

9. The semiconductor device according to claim 7, wherein said first layer comprises a high melting point metal silicide layer.

10. The semiconductor device according to claim 9, wherein said first layer further comprises a barrier metal which is inserted between said high melting point metal silicide layer and said part of said first layer.