Device for detecting a plurality of signal levels indicating stopping of a clock signal

• US 5,936,452 A
• Filed: 10/18/1996
• Issued: 08/10/1999
• Est. Priority Date: 06/03/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Semiconductor Software Company Limited
• Inventors: Asano, Masahiro, Cho, Yoshiki, Utsuno, Masayuki
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/735,079
• Time in Patent Office: 1,026 Days
• Field of Search: 327/18, 327/20, 327/142, 327/292, 327/198
• US Class Current: 327/292
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit

Abstract

The oscillation-stop detecting device accurately detects the stopping of a clock signal due to various causes. The voltage detecting circuit detects when a clock signal output from the clock signal oscillator remains at a high, a low or an intermediate level, and outputs a clock voltage detection signal. The oscillation-stop detecting circuit outputs a detection signal in response to the voltage detection signal.

Claims

1. A device for detecting a plurality of signal levels indicating stopping of a clock signal in a semiconductor device having a clock signal oscillator, the device comprising:

a voltage detecting circuit for outputting a clock voltage detection signal when a clock signal output from a clock signal oscillator remains at a high level, when the clock signal remains at a low level, and when the clock signal remains at an intermediate level; and

an oscillation-stop detecting circuit for outputting a stop detection signal, indicating stopping of the clock signal, in response to the clock voltage detection signal.

2. The device according to claim 1, comprising an oscillation-stop detection controlling circuit for producing an output signal for preventing operation of said oscillation-stop detecting circuit.

3. The device according to claim 1, comprising a reset circuit for generating a reset signal for resetting portions of said semiconductor device when the detection signal from said oscillation-stop detecting circuit becomes active.

4. The device according to claim 1, comprising:

a plurality of clock signal oscillators outputting respective clock signals;

a plurality of voltage detecting circuits for outputting respective clock voltage detection signals when the clock signals output from said plurality of clock signal oscillators remain at any of the high level, the low level, and the intermediate level;

a plurality of oscillation-stop detecting circuits for outputting, in response to the clock voltage detection signals, stop detection signals indicating stopping of the clock signals; and

a register for storing condition information of the stop detection signals, the condition information indicating whether the clock signal output from each of said clock signal oscillators has stopped.

5. The device according to claim 2, comprising a reset circuit for generating a reset signal for resetting portions of said semiconductor device when the detection signal from said oscillation-stop detecting circuit becomes active.

6. The device according to claim 2, comprising:

a plurality of clock signal oscillators outputting respective clock signals;

a plurality of voltage detecting circuits for outputting respective clock voltage detection signals when the clock signals output from said plurality of clock signal oscillators remain at any of the high level, the low level, and the intermediate level;

a plurality of oscillation-stop detecting circuits for outputting, in response to the clock voltage detection signals, stop detection signals indicating stopping of the clock signals; and

a register for storing condition information of the stop detection signals, the condition information indicating whether the clock signal output from each of said clock signal oscillators has stopped.

7. The device according to claim 3, comprising:

a plurality of clock signal oscillators outputting respective clock signals;

a plurality of voltage detecting circuits for outputting respective clock voltage detection signals when the clock signals output from said plurality of clock signal oscillators remain at any of the high level, the low level, and the intermediate level;

a plurality of oscillation-stop detecting circuits for outputting, in response to the clock voltage detection signals, stop detection signals indicating stopping of the clock signals; and

a register for storing condition information of the stop detection signals, the condition information indicating whether the clock signal output from each of said clock signal oscillators has stopped.

8. The device according to claim 2, wherein said oscillation-stop detection controlling circuit blocks operation of said oscillation-stop detecting circuit in response to one of:

(i) a delayed signal generated by delaying a reset signal for resetting said semiconductor device,

(ii) a signal generated by delaying a signal corresponding to a clock stop mode for stopping the clock signal, and

(iii) an active state of a signal for preventing operation of a clock signal-stop detecting function.

9. The device according to claim 8, comprising a reset circuit for generating a reset signal for resetting portions of said semiconductor device when the detection signal from said oscillation-stop detecting circuit becomes active.

10. The device according to claim 8, comprising:

a plurality of clock signal oscillators outputting respective clock signals;

a plurality of voltage detecting circuits for respective outputting clock voltage detection signals when the clock signals output from said plurality of clock signal oscillators remain at any of the high level, the low level, and the intermediate level;

a plurality of oscillation-stop detecting circuits for outputting, in response to the clock voltage detection signals, stop detection signals indicating stopping of the clock signals in response to the clock voltage detection signals; and

a register for storing condition information of the stop detection signals, the condition information indicating whether the clock signal output from each of said clock signal oscillators has stopped.

11. The device according to claim 9, comprising:

a plurality of clock signal oscillators outputting respective clock signals;

a plurality of voltage detecting circuits for respective outputting clock voltage detection signals when the clock signals output from said plurality of clock signal oscillators remain at any of the high level, the low level, and the intermediate level;

a plurality of oscillation-stop detecting circuits for outputting, in response to the clock voltage detection signals, stop detection signals indicating stopping of the clock signals in response to the clock voltage detection signals; and

a register for storing condition information of the stop detection signals, the condition information indicating whether the clock signal output from each of said clock signal oscillators has stopped.

12. The device according to claim 1, wherein the voltage detecting circuit comprises:

a first stop detecting circuit for producing a first stop detecting signal when the clock signal output from said clock signal oscillator remains at the high level;

a second stop detecting circuit for producing a second stop detecting signal when the clock signal output from said clock signal oscillator remains at the low level;

a third stop detecting circuit for producing a third stop detecting signal when the clock signal output from said clock signal oscillator remains at the intermediate level; and

a logic circuit for producing the clock voltage detection signal in response to at least one of the first, second, and third stop detecting signals.

13. The device according to claim 2, wherein the oscillation-stop detecting circuit comprises:

a first transistor for receiving the clock voltage detection signal;

a second transistor for receiving the output signal from the oscillation-stop detection controlling circuit; and

a capacitor coupled to said first and second transistors, wherein said first and second transistors repeatedly charge and discharge said capacitor when the output signal from said oscillation-stop detection controlling circuit is active and the clock signal is operating, and said first and second transistors discharge said capacitor to produce the stop detection signal when the output signal from said oscillation-stop detection controlling circuit is active and the clock signal is not operating.