Apparatus and methods for digitally compensated multi-bit sigma-delta analog-to-digital conversion

• US 5,936,561 A
• Filed: 12/23/1996
• Issued: 08/10/1999
• Est. Priority Date: 12/23/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seong-Ho
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/772,458
• Time in Patent Office: 960 Days
• Field of Search: 341/143, 341/118, 341/120, 341/142, 341/122, 341/110, 341/144, 341/155
• US Class Current: 341/143
• CPC Class Codes: H03M 3/388 by storing corrected or correction values in one or more digital look-up tables
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one

Abstract

A digitally compensated multi-bit sigma-delta analog-to-digital converter may be used to achieve high resolution in analog-to-digital conversions using a low oversampling ratio and simplified hardware construction. The digitally compensated multi-bit sigma-delta analog-to-digital converter has a recycling converter which converts an analog signal to a digital signal and which recycles the converted signal at least one time through a sample hold circuit, an analog-to-digital converter and a digital-to-analog converter in order to obtain a 4 bit digital signal. A digital corrector converts the 4 bit digital signal to a 16 bit corrected digital signal. The 16 bit corrected digital signal is used to generate a digitally compensated digital signal and to generate a digital error code. The digitally compensated digital signal is obtained by adding the 16 bit corrected digital signal with a 16 bit calibrated digital signal using an adder. The nine least significant bits of the compensated digital signal, representing a calibration value indicative of the error in the converted digital signal, are obtained using a roundoff circuit and stored in memory. As a result, high resolution in analog-to-digital conversion can be obtained while achieving a low oversampling ratio and simplified hardware construction.

Claims

1. A digitally compensated multi-bit analog-to-digital converter comprising:

recycling converter means for repeatedly converting to a digital signal the difference between an input analog signal and a reconstructed prior input analog signal, said reconstructed prior input analog signal comprising a prior input analog signal which has been converted to a digital signal and has been reconverted back to an analog signal to obtain a recycled digital signal;

a digital corrector which is responsive to said recycling converter means, and which digitally corrects said recycled digital signal to obtain a digitally corrected digital signal; and

a digital calibrator which is responsive to said digital corrector, to generate a digitally compensated digital signal and to generate a digital error code, wherein said digital calibrator comprises;

a calibrating circuit which is responsive to said digital corrector, and which obtains a digitally calibrated digital signal; and

a combiner which combines the digitally calibrated digital signal and the digitally corrected digital signal to generate a digitally compensated digital signal; and

a rounder which is responsive to said combiner, and which generates a digital error code.

2. A digitally compensated multi-bit analog-to-digital converter according to claim 1 further comprising a clock, and wherein said recycling converter means and said digital calibrator are responsive to said clock.

3. A digitally compensated multi-bit analog-to-digital converter according to claim 1 wherein said recycling converter means comprises:

a sample-hold circuit which samples an analog input signal to obtain a sampled analog signal;

an analog-to-digital converter which is responsive to said sample-hold circuit, and which converts the sampled analog signal to a digital signal;

a multi-bit digital-to-analog converter which is responsive to said analog-to-digital converter, and which generates a reconstructed analog signal from said digital signal; and

an adder which adds said reconstructed analog signal to said analog input signal.

4. A digitally compensated multi-bit analog-to-digital converter according to claim 3 wherein said analog-to-digital converter is a flash type analog-to-digital converter.

5. A digitally compensated multi-bit analog-to-digital converter according to claim 1 wherein said digital calibrator further comprises a memory which stores the digital error code.

6. A digitally compensated multi-bit analog-to-digital converter according to claim 1 wherein said combiner comprises an adder which adds the digitally calibrated digital signal and the digitally corrected digital signal to generate a digitally compensated digital signal, and a register which stores the digitally compensated digital signal.

7. A digitally compensated multi-bit analog-to-digital converter according to claim 1 wherein said digitally compensated multi-bit analog-to-digital converter is a sigma-delta analog-to-digital converter.

8. A digitally compensated multi-bit analog-to-digital converter according to claim 1, wherein said recycling converter means comprises means for repeatedly converting a first analog signal to a digital signal, converting the digital signal to a first generated analog signal which is subtracted from the first analog signal to provide a summed analog signal which is converted to a second digital signal which is converted to a second generated analog signal which is summed with the first analog signal to provide a second summed analog signal which is converted to a digital signal to obtain said recycled digital signal.

9. A digitally compensated multi-bit sigma-delta analog-to-digital converter comprising:

a sample-hold circuit which samples the difference between an input signal and a re-constructed analog signal at a first clock, which holds the sampled input signal at a second clock signal and which outputs the sampled difference between the input signal and the re-constructed analog signal;

an analog-to-digital converter which receives the output of said sample-hold circuit, and which converts the difference between the input signal and the re-constructed analog signal to a digital signal in response to the second clock signal;

a multi-bit digital-to-analog converter which receives the digital signal from the analog-to-digital converter, and which generates the re-constructed analog signal from said digital signal;

a digital corrector which is responsive to said analog-to-digital converter, to digitally correct said digital signal;

a digital calibrator which supplies a digitally calibrated digital signal corresponding to the digitally corrected digital signal; and

an adding means which is responsive to said digital corrector and said digital calibrator, and which adds the digitally corrected digital signal to the digitally calibrated digital signal to generate a digitally compensated digital signal.

10. A digitally compensated multi-bit sigma-delta analog-to-digital converter according to claim 9 wherein said digital calibrator comprises:

a round-off circuit, which is responsive to said adder, and which generates a calibrated value by rounding off said digitally compensated digital signal;

a memory which stores the calibrated value in response to said digital correcter and in response to a write control signal; and

a register which is responsive to said adder and the second clock signal, to store the digitally compensated digital signal.

11. A method for converting an analog signal to a digitally compensated multi-bit digital signal comprising the steps of:

repeatedly converting the difference between an analog input signal and a reconstructed analog signal to a digital signal to obtain a recycled digital signal;

digitally correcting said recycled digital signal to obtain a digitally corrected digital signal; and

calibrating said digitally corrected digital signal to generate a digitally compensated digital signal and to generate a digital error code, wherein said calibrating step comprises the steps of;

obtaining a digitally calibrated digital signal;

combining the digitally calibrated digital signal and the digitally corrected digital signal to generate a digitally compensated digital signal; and

rounding off the digitally compensated digital signal to generate a digital error code.

12. A method according to claim 11 further comprising the step of controlling said repeatedly converting step and said calibrating step with a clocking signal.

13. A method according to claim 11 wherein said repeatedly converting step comprises the steps of:

sampling an analog input signal to obtain a sampled analog signal;

converting the sampled analog signal to a digital signal;

converting the digital signal to a reconstructed analog signal; and

adding said reconstructed analog signal to said analog input signal.

14. A method according to claim 13 wherein said sampled analog signal converting step utilizes a flash type analog-to-digital converter.

15. A method according to claim 11 wherein said calibrating step further comprises the step of storing the digital error code in a memory.

16. A method according to claim 11 wherein said combining step comprises the steps of adding the digitally calibrated digital signal and the digitally corrected digital signal to generate a digitally compensated digital signal and storing the digitally compensated digital signal in a register.

17. A method for converting an analog signal to a digitally compensated multi-bit digital signal comprising the steps of:

sampling a difference between an input analog signal and a re-constructed analog signal at a first clock signal;

holding the sampled difference between the input analog signal and the reconstructed analog signal at a second clock signal;

converting the held sampled difference between the input analog signal and the reconstructed analog signal to a digital signal in response to the second clock signal;

generating a reconstructed analog signal from said digital signal;

digitally correcting said digital signal to obtain a digitally corrected digital signal;

supplying a digitally calibrated digital signal corresponding to the digitally corrected digital signal; and

adding the digitally corrected digital signal to the digitally calibrated digital signal to generate a digitally compensated digital signal.

18. A method according to claim 17 further comprising the steps of:

rounding off said digitally compensated digital signal to obtain a calibrated value;

storing the calibrated value in a memory; and

storing the digitally compensated digital signal in a register.