High-speed sigma-delta ADCs

• US 5,936,562 A
• Filed: 06/06/1997
• Issued: 08/10/1999
• Est. Priority Date: 06/06/1997
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Brooks, Todd L., Robertson, David
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/870,429
• Time in Patent Office: 795 Days
• Field of Search: 341/143, 341/155, 341/200
• US Class Current: 341/143
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 3/46 using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type

Abstract

An ADC system includes a sigma-delta modulator that receives an analog input and provides a first digital output and an analog output. An ADC, coupled to the sigma-delta modulator, receives the analog output as an input and provides a second digital output. A digital processor, coupled to the sigma-delta modulator and the ADC, receives the first and second digital outputs and provides a digital representation of the analog input.

Claims

1. An ADC system comprising:

a sigma-delta modulator that receives an analog input and provides a first digital output and an analog output;

a non-sigma-delta ADC, coupled to the sigma-delta modulator, that receives the analog output as an input and provides a second digital output; and

a digital processor, coupled to the sigma-delta modulator and the non-sigma-delta ADC, that receives the first and second digital outputs and provides a digital representation of the analog input.

2. The ADC system as claimed in claim 1 wherein the sigma-delta modulator includes a quantizer ADC.

3. The ADC system as claimed in claim 2 wherein the non-sigma-delta ADC has a throughput delay greater than that of the quantizer ADC.

4. The ADC system as claimed in claim 2 wherein the non-sigma-delta ADC has higher resolution than the quantizer ADC.

5. The ADC system as claimed in claim 1 wherein the non-sigma-delta ADC includes a pipeline ADC.

6. The ADC system as claimed in claim 5 wherein the sigma-delta modulator includes a quantizer ADC which forms a portion of the pipeline ADC.

7. The ADC system as claimed in claim 1 wherein the non-sigma-delta ADC includes a parallel time-interleaved ADC.

8. The ADC system as claimed in claim 7 wherein the sigma-delta modulator includes a quantizer ADC which forms a portion of the parallel time-interleaved ADC.

9. The ADC system as claimed in claim 1 wherein the first digital output is coupled to the digital processor with a delay element.

10. The ADC system as claimed in claim 1 wherein the sigma-delta modulator includes a multi-bit feedback loop.

11. The ADC system as claimed in claim 10 wherein the sigma-delta modulator further includes a digital data scrambler in the multi-bit feedback loop.

12. The ADC system as claimed in claim 1 wherein the digital processor includes a digital combiner that combines two digital signals equal to, or derived from, the first and second digital outputs.

13. The ADC system as claimed in claim 1 wherein the digital processor includes a digital filter having a transfer function with at least one term that approximates an analog transfer function of the sigma-delta modulator.