Accelerated graphics port memory mapped status and control registers

• US 5,936,640 A
• Filed: 09/30/1997
• Issued: 08/10/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Elliott, Robert C., Lester, Robert Allan, Jones, Phillip M., Santos, Gregory N., Horan, Ronald T.
• Primary Examiner(s): Chauhan, U.
• Application Number:
  US08/941,862
• Time in Patent Office: 679 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/508, 345/511, 345/512, 345/203, 345/516, 345/681, 345/682, 345/280, 345/284, 345/309, 345/310, 395/828, 395/829, 395/830, 395/839, 395/843, 395/874, 395/875, 395/892, 711/100, 711/117, 711/118, 711/135, 711/144, 711/145, 711/200, 711/202, 711/203, 711/205, 711/209, 711/221
• US Class Current: 345/531
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

Claims

1. A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) processor, said system comprising:

a system processor executing software instructions and generating graphics data;

a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;

the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage, the starting address for each of the plurality of pages of graphics data being stored in a graphics address re-mapping table (GART) located in said system memory;

an accelerated graphics port (AGP) processor, said AGP processor generating video display data from the graphics data for display on a video display;

a core logic chipset supporting GART features;

said core logic chipset having a first interface logic for connecting said system processor to said system memory;

said core logic chipset having a second interface logic for connecting said system processor and said system memory to said AGP processor;

said core logic chipset having a third interface logic for connecting said system processor and said system memory to input-output devices on a peripheral component interconnect (PCI) bus;

said core logic chipset having a fourth interface logic for connecting said AGP processor to said PCI bus;

a GART cache in said core logic chipset;

a GART cache entry control register used to update/invalidate a specific GART entry in said GART cache;

said GART cache entry control register being stored in said system memory, wherein said GART cache entry control register is accessed from the system memory using a base address stored in a base address resister of said core logic chipset; and

said GART cache entry control register comprising;

a GART entry offset first portion specifies the AGP device address of a GART entry in said GART cache to be invalidated/updated;

a GART cache entry update second portion, when set to a first logic level, causes said core logic chipset to replace the GART entry in said GART cache, specified by the GART entry offset first portion, with a more current entry stored in the GART in said system memory; and

a GART cache entry invalidate third portion, when set to the first logic level, causes said core logic chipset to invalidate the GART entry in said GART cache specified by the GART entry offset first portion.

2. The computer system of claim 1, wherein the base address register is part of said third interface logic.

3. The computer system of claim 1, further comprising a GART directory cache.

4. The computer system of claim 3, further comprising a GART directory/table cache control register which is used to invalidate the contents of said GART cache and said GART cache.

5. The computer system of claim 1, wherein the base address is determined by and written to said base address register by a basic input-output operating system program of the computer system.

6. The computer system of claim 1, wherein said GART cache entry control register is used by a GART miniport driver software to control the functionality within said core logic chipset during operation of the computer system.

7. The computer system of claim 1, further comprising a revision identification register which identifies the format and features supported by said core logic chipset.

8. The computer system of claim 7, wherein said revision identification register contains an AGP interface specification supplement revision number which said core logic chipset conforms thereto.

9. The computer system of claim 3, further comprising a GART table/directory base address register which is used to store a physical address for a GART directory in said system memory when a two-level GART address translation is used.

10. The computer system of claim 1, wherein said AGP memory-mapped status and control registers comprise! further comprising a GART capabilities register which defines the GART features supported by said core logic chipset, said GART capabilities register comprising:

an AGP bus utilization, bandwidth, and latency supported first portion, when set to a first logic level, indicates that the core logic chipset is capable of performing AGP bus utilization, bandwidth, and latency calculations;

an address translation level supported second portion indicating whether single-level or two-level address translation is supported by the core logic chipset, wherein when the second portion is set to a first logic level a two-level address translation is supported, and when the second portion is set to a second logic level a single-level address translation is supported;

a GART entry linking supported third portion, when set to the first logic level, indicates that the core logic chipset is capable of using a predefined link bit in each GART entry to determine whether to cache the next contiguous GART entry; and

a valid bit error reporting supported fourth portion, when set to the first logic level, indicates that the core logic chipset is capable of generating a system error (SERR#) when an AGP graphics device attempts to access an invalid page in said system memory.

11. The computer system of claim 1, further comprising an AGP feature control register used to enable the GART features supported by said core logic chipset, said AGP feature control register comprising:

a GART cache enable first portion, when set to a first logic level, enables GART caching and, when set to a second logic level, disables GART caching;

a GART entry linking enable second portion, when set to the first logic level, indicates that the core logic chipset will use a predefined link bit in each GART entry to determine whether to cache the next contiguous GART entry; and

a valid bit error reporting enable third portion, when set to the first logic level, enables the core logic chipset to generate a systems error (SERR#) when an AGP graphics device attempts to access an invalid page in said system memory.

12. The computer system of claim 1, further comprising an AGP feature status register which is used to record status information for AGP and GART related events, said AGP feature status register having a valid bit error detected portion, when set to a first logic level, indicates a valid bit error has been detected and a system error (SERR#) has been generated by said core logic chipset.

13. The computer system of claim 12, wherein the valid bit error detected portion will toggle to a second logic level when the first logic level is written thereto.

14. The computer system of claim 1, further comprising a GART table/directory base address register which is used to store a physical address for said GART in said system memory when a single-level GART address translation is used.

15. The computer system of claim 3, further comprising a GART directory/table cache size register which is used to indicate the maximum number of GART entries and GART directory entries that may be cached, said GART directory/table cache size register comprising:

a first portion which indicates a maximum number of GART directory entries which may be cached by the core logic chipset; and

a second portion which indicates a maximum number of GART entries which may be cached by the core logic chipset.

16. The computer system of claim 1, further comprising a posted write buffer control register wherein a first logic level written to said posted write buffer control register causes said core logic chipset to flush its processor to memory posted write buffers.

17. The computer system of claim 1, further comprising an AGP bus utilization/bandwidth/latency command register for controlling AGP bus utilization, bandwidth, and latency counters in said core logic chipset, said AGP bus utilization/bandwidth/latency command register comprising:

an enable AGP bus latency counter first portion, when set to a first logic level, starts an AGP bus latency register counter, and when set to a second logic level, stops said AGP bus latency register counter;

an enable AGP bus bandwidth counter second portion, when set to the first logic level, starts an AGP bus bandwidth register counter, and when set to the second logic level, stops said AGP bus bandwidth register counter;

an enable AGP bus utilization counter third portion, when set to the first logic level, starts an AGP bus utilization register counter, and when set to the second logic level, stops said AGP bus utilization register counter; and

a clear AGP bus utilization counters fourth portion, when set to the first logic level, clears said AGP bus latency register counter, said AGP bus bandwidth register counter, and said AGP bus utilization register counter to a zero value.

18. The computer system of claim 17, wherein said AGP bus utilization register counter increments for each AGP bus clock during selected AGP bus activities.

19. The computer system of claim 17, wherein said AGP bus bandwidth register counter increments for each AGP bus clock during other selected AGP bus activities.

20. The computer system of claim 17, wherein said AGP bus latency register counter increments for each AGP bus clock that expires while said core logic chipset is processing a particular AGP read request, wherein said AGP bus latency register counter starts counting when the AGP read request is enqueued and stops counting when a first quad word of data is returned.

21. The computer system of claim 1, wherein said system processor is a plurality of system processors.

22. The computer system of claim 1, wherein said core logic chipset is at least one integrated circuit.

23. The computer system of claim 22, wherein the at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

24. The computer system of claim 22, wherein the at least one integrated circuit core logic chipset is at least one programmable logic array integrated circuit.

25. The computer system of claim 1, further comprising a video display.

26. The computer system of claim 1, further comprising a network interface card, a hard disk, a floppy disk drive, a modem, a keyboard, and a mouse.

27. The computer system of claim 1, further comprising a serial port, a parallel port, a keyboard and a real time clock.

28. The computer system of claim 1, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

29. A method, in a computer system having a core logic chipset which connects a host processor and main memory to an accelerated graphics port (AGP) processor, for controlling the functionality of the core logic chipset, said method comprising the steps of:

storing a plurality of accelerated graphics port (AGP) memory-mapped status and control registers in a computer system main memory;

accessing the plurality of AGP memory-mapped status and control registers stored in the main memory using a base address stored in a base address register of a host-to-peripheral bus bridge;

reading from and writing to the plurality of AGP memory-mapped status and control registers stored in the computer system memory with a software program for controlling the functionality of a core logic chipset during operation of the computer system, wherein the steps of reading from and writing to the plurality of AGP memory-mapped status and control registers, comprises the steps of;

reading from and writing to a graphics address re-mapping table (GART) cache entry control register for updating/invalidating a specific GART entry in a GART cache of the core logic chipset, wherein the step of writing to the GART cache entry control register, comprises the steps of;

writing an AGP device address to a GART entry offset first portion of the GART cache entry control register for determining a GART entry in the GART cache to be invalidated/updated; and

writing a first logic level to a GART cache entry update second portion of the GART cache entry control register to cause the core logic chipset to updated the GART entry in the GART cache, specified by the GART entry offset first portion, with a more current entry from a GART in the computer system memory.

30. The method of claim 29, further comprising the step of writing the base address to the base address register with a basic input-output operating system program of the computer system.

31. The method of claim 29, wherein the software program is a graphics address re-mapping table (GART) miniport driver software.

32. The method of claim 29, further comprising the step of reading a revision identification register to identify the format and features provided by said AGP memory-mapped status and control registers.

33. The method of claim 32, further comprising the step of reading from the revision identification register an AGP interface specification supplement revision number that the core logic chipset complies therewith.

34. The method of claim 29, further comprising the steps of reading from and writing to a GART capabilities register which defines the GART features supported by the core logic chipset.

35. The method of claim 34, wherein the step of reading from the GART capabilities register, comprises the steps of:

reading an AGP bus utilization, bandwidth, and latency supported first portion of the GART capabilities register for determining if the core logic chipset is capable of performing AGP bus utilization, bandwidth, and latency calculations;

reading an address translation level supported second portion of the GART capabilities register for determining if single-level or two-level address translation is supported by the core logic chipset;

reading a GART entry linking supported third portion of the GART capabilities register for determining if the core logic chipset is capable of using a predefined link bit in each GART entry in determining whether to cache the next contiguous GART entry; and

reading a valid bit error reporting supported fourth portion of the GART capabilities register for determining if the core logic chipset is capable of generating a system error (SERR#) when an AGP graphics device attempts to access an invalid page in the system memory.

36. The method of claim 35, wherein the step of writing to the GART capabilities register, comprises the steps of:

writing a first logic level to the AGP bus utilization, bandwidth, and latency supported first portion if the core logic chipset is capable of performing AGP bus utilization, bandwidth, and latency calculations, otherwise, writing a second logic level thereto;

writing the first logic level to the address translation level supported second portion if two-level address translation is supported by the core logic chipset, otherwise, writing the second logic level thereto if single-level address translation is supported;

writing the first logic level to the GART entry linking supported third portion if the core logic chipset is capable of using a predefined link bit in each GART entry in determining whether to cache the next contiguous GART entry; and

writing the first logic level to the valid bit error reporting supported fourth portion if the core logic chipset is capable of generating a system error (SERR#) when an AGP graphics device attempts to access an invalid page in the system memory.

37. The method of claim 29, further comprising the steps of reading from and writing to an AGP feature control register for enabling the GART features supported by the core logic chipset.

38. The method of claim 37, wherein the step of reading from the AGP feature control register, comprises the steps of:

reading a GART cache enable first portion for determining if GART caching is enabled;

reading a GART entry linking enable second portion for determining if the core logic chipset will use a predefined link bit in each GART entry to determine whether to cache the next contiguous GART entry; and

reading a valid bit error reporting enable third portion for determining if the core logic chipset will generate a systems error (SERR#) when an AGP graphics device attempts to access an invalid page in said system memory.

39. The method of claim 38, wherein the step of writing to the AGP feature control register, comprises the steps of:

writing a first logic level to the GART cache enable first portion to enable GART caching, and writing a second logic level thereto to disable the GART caching;

writing the first logic level to the GART entry linking enable second portion to enable the core logic chipset to use a predefined link bit in each GART entry to determine whether to cache the next contiguous GART entry, and writing the second logic level thereto to disable the use of the predefined link bit; and

writing the first logic level to the valid bit error reporting enable third portion to enable the core logic chipset to generate a systems error (SERR#) when an AGP graphics device attempts to access an invalid page in the system memory, and writing the second logic level thereto to disable generation of SERR#.

40. The method of claim 29, further comprising the steps of reading from and writing to an AGP feature status register for recording status information for AGP and GART related events.

41. The method of claim 40, wherein the step of reading from the AGP feature status register comprises the step of reading a valid bit error detected portion of the AGP feature status register for determining if a first logic level is present which indicates that a valid bit error has been detected and a system error (SERR#) has been generated by the core logic chipset.

42. The method of claim 41, wherein the step of writing to the AGP feature status register comprises the step of writing the first logic level to the valid bit error detected portion so as to toggle the first logic level therein to a second logic level.

43. The method of claim 29, further comprising the steps of reading from and writing to a GART table/directory base address register which is used to store a physical address for the GART in the system memory when a single-level GART address translation is used.

44. The method of claim 29, further comprising the steps of reading from and writing to a GART table/directory base address register which is used to store a physical address for a GART directory in the main memory when a two-level GART address translation is used.

45. The method of claim 29, further comprising the steps of reading from and writing to a GART directory/table cache size register for indicating the maximum number of GART entries and GART directory entries that may be cached.

46. The method of claim 45, wherein the step of reading from the GART directory/table cache size register, comprises the steps of:

reading a first portion of the GART directory/table cache size register to determine a maximum number of GART directory entries which may be cached by the core logic chipset; and

reading a second portion of the GART directory/table cache size register to determine a maximum number of GART entries which may be cached by the core logic chipset.

47. The method of claim 45, wherein the step of writing to the GART directory/table cache size register, comprises the steps of:

writing a first value to the first portion of the GART directory/table cache size register, wherein the first value represents the maximum number of GART directory entries which may be cached by the core logic chipset; and

writing a second value to the second portion of the GART directory/table cache size register, wherein the second value represents the maximum number of GART entries which may be cached by the core logic chipset.

49. The method of claim 29, wherein the step of writing to the GART cache entry control register, further comprises the step of:

writing a GART cache entry invalidate third portion of the GART cache entry control register to cause the core logic chipset to invalidated the GART entry in the GART cache, specified by the GART entry offset first portion.

50. The method of claim 49, wherein the step of reading from the GART cache entry control register, comprises the steps of:

reading the GART entry offset first portion to determine the AGP device address written therein of a GART entry in the GART cache to be invalidated/updated;

reading the GART cache entry update second portion to determine that the core logic chipset has updated the GART entry in the GART cache, specified by the GART entry offset first portion, with a more current entry of the GART in the computer system memory; and

reading the GART cache entry invalidate third portion to determine that the core logic chipset has invalidated the GART entry in the GART cache, specified by the GART entry offset first portion.

51. The method of claim 29, further comprising the steps of reading from and writing to a posted write buffer control register wherein a first logic level written to the posted write buffer control register causes the core logic chipset to flush its processor to memory posted write buffers.

52. The method of claim 51, wherein the step of reading from the posted write buffer control register a second logic level indicates that the core logic chipset has flushed its processor to memory posted write buffers.

53. The method of claim 29, further comprising the steps of reading from and writing to an AGP bus utilization/bandwidth/latency command register for controlling AGP bus utilization, bandwidth, and latency counters in the core logic chipset.

54. The method of claim 53, wherein the step of writing to the AGP bus utilization/bandwidth/latency command register, comprises the steps of:

writing a first logic level to an enable AGP bus latency counter first portion of the AGP bus utilization/bandwidth/latency command register starts an AGP bus latency register counter;

writing a second logic level to the enable AGP bus latency counter first portion stops the AGP bus latency register counter;

writing the first logic level to an enable AGP bus bandwidth counter second portion of the AGP bus utilization/bandwidth/latency command register starts an AGP bus bandwidth register counter;

writing the second logic level to the enable AGP bus bandwidth counter second portion stops the AGP bus bandwidth register counter;

writing the first logic level to an enable AGP bus utilization counter third portion of the AGP bus utilization/bandwidth/latency command register starts an AGP bus utilization register counter;

writing the second logic level to the enable AGP bus utilization counter third portion stops the AGP bus utilization register counter; and

writing the first logic level to a clear AGP bus utilization counters fourth portion of the AGP bus utilization/bandwidth/latency command register clears the AGP bus latency register counter, the AGP bus bandwidth register counter, and the AGP bus utilization register counter to a zero value.

55. The method of claim 54, wherein the step of reading from the AGP bus utilization/bandwidth/latency command register, comprises the steps of:

reading the enable AGP bus latency counter first portion to determine if the AGP bus latency register counter is counting;

reading the enable AGP bus bandwidth counter second portion to determine if the AGP bus bandwidth register counter is counting;

reading the enable AGP bus utilization counter third portion to determine if the AGP bus utilization register counter is counting.

56. The method of claim 55, further comprising the step of reading a value from the AGP bus utilization register counter, the value indicating the number of AGP clock cycles a sideband address (SBA) bus is being used for enqueuing requests versus the total number of clock cycles within a sampling period when running SBA mode.

57. The method of claim 55, further comprising the step of reading a value from the AGP bus bandwidth register counter, the value indicating the percentage of time data is being transferred on the address-data bus.

58. The method of claim 55, further comprising the step of reading a value from the AGP bus latency register counter which increments for each AGP bus clock that expires while the core logic chipset is processing a particular AGP read request, wherein the AGP bus latency register counter starts counting when the AGP read request is enqueued and stops counting when a first quad word of data is returned from the main memory.

48. The method of claim 48, further comprising the steps of reading from and writing to a GART directory/table cache control register which is used to invalidate the contents of a GART cache and a GART directory cache in the core logic chipset when a first logic level is written thereto.