Multi-mode, multi-channel communication bus

• US 5,936,953 A
• Filed: 12/18/1997
• Issued: 08/10/1999
• Est. Priority Date: 12/18/1997
• Status: Expired due to Fees

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Simmons, Albert L.
• Primary Examiner(s): Patel, Ajit
• Assistant Examiner(s): Pizarro, Ricardo M.
• Application Number:
  US08/993,642
• Time in Patent Office: 600 Days
• Field of Search: 370/362, 370/364, 370/365, 370/241, 370/254, 370/257, 395/293, 395/306, 395/307, 395/308, 395/309, 395/886
• US Class Current: 370/364
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A dynamically reconfigurable, multi-mode, multi-channel communication bus. The bus may be dynamically reconfigured into a plurality fo segments, or slices, to provide a relatively wide unified bus, or smaller versions of the bus. This allows multiple bus masters to coexist at the same time that control the bus. The protocol is adaptive in that bus widths dynamically change to allow addition or removal of bus masters at any time. Bus acquisition delays caused by bus arbitration latency using a packetized protocol regime are drastically reduced or eliminated in some systems by using the present bus. The bus demonstrates relatively high efficiency.

Claims

1. A communication bus that permits communication between a plurality of nodes and which permits multiple nodes to drive the bus at the same time, said communication bus comprising:

a bus interface disposed in each of the nodes, wherein said each of the nodes comprises

(i) an input port comprising an input resister with a data input having a relatively wide data path,

(ii) a barrel shift registered coupled to the input register,

(iii) a shift register controller coupled to the barrel shift register for controlling the barrel shift register,

(iv) a plurality of shift registers coupled to the barrel shift register so that each shift register of the plurality of shift registers has a data path that has a predetermined width that is less than the relatively wide data path,

(v) a latch coupled to the plurality of shift registers,

(vi) a latch controller coupled to the plurality of shift registers and the latch for controlling movement of addresses and data therethrough, and

(vii) a data register coupled to the latch that comprises a data output having a data path with a predetermined width that is less than the relatively wide data path;

a plurality of multiplexed busses coupled between the bus interfaces of said each of the nodes so that each bus of said plurality of multiplexed busses has a bus width that is a predetermined portion of the communication bus, and whose combined bus width is equal to the bus width of the communication bus;

a plurality of control lines coupled between the bus interfaces of each of the nodes; and

wherein one of the nodes includes an arbiter comprising logic that dynamically reconfigures the bus width of the communication bus to segment the communication bus into smaller independent slices and to allow multiple bus masters to control individual segments of the bus at the same time.

2. The communication bus of claim 1 wherein the plurality of nodes comprise a plurality of application specific integrated circuits.

3. The communication bus of claim 1 wherein the plurality of control lines further comprise a plurality of idle lines coupled between said each of the nodes.

4. A communication bus that permits communication between a plurality of nodes and which permits multiple nodes to drive the bus at the same time, said communication bus comprising:

a bus interface disposed in each of the nodes;

a plurality of multiplexed busses coupled between the bus interfaces of each of the nodes so that each bus of said plurality of multiplexed busses has a bus width that is a predetermined portion of the communication bus, and whose combined bus width is equal to the bus width of the communication bus;

a plurality of control lines coupled between the bus interfaces of each of the nodes;

wherein one of the nodes includes a arbiter comprising logic that dynamically reconfigures the bus width of the communication bus to segment the communication bus into smaller independent slices and to allow multiple bus masters to communication individual segments of the bus at the same time; and

wherein the plurality of control lines comprises;

(i) a plurality of bus node lines coupled between the arbiter and each of the other nodes,

(ii) a plurality of bus request and grant lines coupled between each of the nodes, and

(iii) a plurality of read/write lines coupled between said each of the nodes.

5. The communication bus of claim 4 wherein the plurality of nodes comprise a plurality of application specific integrated circuits.