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Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof

  • US 5,937,193 A
  • Filed: 11/27/1996
  • Issued: 08/10/1999
  • Est. Priority Date: 11/27/1996
  • Status: Expired due to Term
First Claim
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1. A computer system for executing program code in a format having platform-independent instructions, the computer system comprising:

  • a processor for executing program code in a format having native instructions;

    a memory coupled to the processor for storing program code for execution by the processor, wherein the memory is a first memory and is coupled to the processor by an address bus and a data bus;

    a vector table and an object table, the object table including a plurality of entries, each entry including at least one native instruction corresponding to one of the platform-independent instructions, and the vector table including a plurality of vectors indexed by the platform-independent instructions, each vector pointing to one of the entries in the object table; and

    a translation circuit coupled to the memory, the translation circuit configured and arranged to receive a platform-independent instruction from the memory and output at least one native instruction for the processor corresponding thereto, wherein the translation circuit further comprises;

    a state machine, coupled to the memory and the vector and object tables, the state machine configured and arranged to receive a block of platform-independent program code stored in the memory and output a block of corresponding native program code to the memory;

    a source address register configured and arranged to store a source address in the memory of a platform-independent instruction to be translated;

    a destination address register configured and arranged to store a destination address in the memory at which to store a native instruction corresponding to the platform-independent instruction pointed to by the source address register;

    an instruction register configured and arranged to store the platform-independent instruction pointed to by the source address register; and

    a translate object address register configured and arranged to store a translate object address pointing to a native instruction stored in the object table that corresponds to the platform-independent instruction pointed to by the source address register;

    wherein the state machine is coupled to the source address register, the destination address register, the instruction register, and the translate object address register, and wherein the state machine is configured and arranged to manipulate the destination address and translate object address registers to store each native instruction, in the entry in the object table corresponding to the platform-independent instruction stored in the instruction register, in the memory starting at the destination address.

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