Circuit arrangement for translating platform-independent instructions for execution on a hardware platform and method thereof

• US 5,937,193 A
• Filed: 11/27/1996
• Issued: 08/10/1999
• Est. Priority Date: 11/27/1996
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Evoy, David Ross
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US08/757,430
• Time in Patent Office: 986 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/704, 395/705
• US Class Current: 717/140
• CPC Class Codes: G06F 8/44 Encoding
• CPC Class Codes: G06F 8/52 Binary to binary
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A translating circuit coupled to a processor and memory of a computer system translates platform-independent instructions such as Java bytecodes into corresponding native instructions for execution by the processor. In one embodiment, the translating circuit is incorporated into the same integrated circuit device as the processor. In another embodiment, the translating circuit is provided within one or more external integrated circuit devices. One or more look-up tables map platform-independent instructions into one or more native instructions for the processor, thereby minimizing software-based interpretation of platform-independent program code. Moreover, platform-independent instructions are mapped to native instructions on-the-fly, or alternatively, in blocks prior to execution using a state machine.

Claims

1. A computer system for executing program code in a format having platform-independent instructions, the computer system comprising:

a processor for executing program code in a format having native instructions;

a memory coupled to the processor for storing program code for execution by the processor, wherein the memory is a first memory and is coupled to the processor by an address bus and a data bus;

a vector table and an object table, the object table including a plurality of entries, each entry including at least one native instruction corresponding to one of the platform-independent instructions, and the vector table including a plurality of vectors indexed by the platform-independent instructions, each vector pointing to one of the entries in the object table; and

a translation circuit coupled to the memory, the translation circuit configured and arranged to receive a platform-independent instruction from the memory and output at least one native instruction for the processor corresponding thereto, wherein the translation circuit further comprises;

a state machine, coupled to the memory and the vector and object tables, the state machine configured and arranged to receive a block of platform-independent program code stored in the memory and output a block of corresponding native program code to the memory;

a source address register configured and arranged to store a source address in the memory of a platform-independent instruction to be translated;

a destination address register configured and arranged to store a destination address in the memory at which to store a native instruction corresponding to the platform-independent instruction pointed to by the source address register;

an instruction register configured and arranged to store the platform-independent instruction pointed to by the source address register; and

a translate object address register configured and arranged to store a translate object address pointing to a native instruction stored in the object table that corresponds to the platform-independent instruction pointed to by the source address register;

wherein the state machine is coupled to the source address register, the destination address register, the instruction register, and the translate object address register, and wherein the state machine is configured and arranged to manipulate the destination address and translate object address registers to store each native instruction, in the entry in the object table corresponding to the platform-independent instruction stored in the instruction register, in the memory starting at the destination address.

2. The computer system of claim 1, wherein entries in the object table include end codes delimiting the end of the entries, and wherein the state machine is configured and arranged to detect the end codes to terminate translation of each platform-independent instruction.

3. The computer system of claim 2, wherein selected entries in the object table further include immediate codes indicating embedded data in the block of platform-independent program code, and wherein the state machine is configured and arranged to detect the immediate codes to store embedded data directly in the corresponding block of native program code.

4. The computer system of claim 1, wherein the platform-independent instruction comprises a Java-type bytecode.

5. The computer system of claim 1, wherein the translation circuit outputs an exception signal to the processor when a platform-independent instruction received by the translation circuit cannot be directly translated to a native instruction.

6. The computer system of claim 1, wherein the vector and object tables are stored in the memory.

7. The computer system of claim 1, wherein the processor and the translation circuit are disposed on the same integrated circuit chip.

8. A translation circuit for use in a computer system to execute program code in a format having platform-independent instructions on a processor in the computer system that executes program code in a format having native instructions, the computer system further including a memory, the translation circuit comprising:

an input circuit configured and arranged to receive a platform-independent instruction, the input circuit including a source address register configured and arranged to store a source address of a platform-independent instruction to be translated;

translating means, coupled to the input circuit, for outputting at least one native instruction for the processor corresponding the platform-independent instruction;

a destination address register configured and arranged to store a destination address in the memory for storing a native instruction corresponding to the platform-independent instruction pointed to by the source address register; and

a block processing means, coupled to the source address register, the destination address register, and the translating means, and configured and arranged to supply a block of platform-independent program code stored in the memory to the translating means and store in the memory a block of corresponding native program code output from the translating means.

9. The translation circuit of claim 8, wherein the input circuit includes an instruction register configured and arranged to store the platform-independent instruction, and wherein the translating means includes a translate object address register storing a vector to an entry in an object table in the memory, the entry including at least one native instruction corresponding to the platform-independent instruction.

10. The translation circuit of claim 9, wherein the translating means further comprises a translation vector base address register configured and arranged to store a starting address for a vector table in the memory, the vector table including a plurality of vectors, each of which points to an entry in the object table, and the vector table indexed by the platform-independent instruction stored in the instruction register.

11. The translation circuit of claim 8, wherein the translating means comprises an object table including a plurality of entries, each entry matching a platform-independent instruction with at least one native instruction for the processor.

12. The translation circuit of claim 11, wherein the translating means further comprises a vector table, indexed by the platform-independent instruction received by the receiving means, the vector table including a plurality of vectors, each of which points to an entry in the object table.

13. The translation circuit of claim 8, wherein the translation circuit is disposed in a single integrated circuit device.

14. The translation circuit of claim 13, wherein the translation circuit is disposed on the same integrated circuit device as the processor of the computer system.

15. The translation circuit of claim 8, wherein the translation circuit is disposed on a circuit board.

16. The translation circuit of claim 15, wherein the translation circuit is disposed on the same circuit board as the processor and the memory of the computer system.

17. The translation circuit of claim 8, wherein the block processing means includes a state machine, the state machine acting as a bus master that controls the bus during translation of the block of platform-independent program code.

18. The translation circuit of claim 8, wherein the platform-independent instruction is a Java bytecode.

19. A computer system for executing program code in a format having platform-independent instructions, the computer system comprising:

a processor for executing program code in a format having native instructions;

a memory coupled to the processor for storing program code for execution by the processor;

a translation circuit coupled to the memory, the translation circuit configured and arranged to receive a platform-independent instruction from the memory and output at least one native instruction for the processor corresponding thereto;

a source address register configured and arranged to store a source address in the memory of a platform-independent instruction to be translated;

a destination address register configured and arranged to store a destination address in the memory for storing a native instruction corresponding to the platform-independent instruction pointed to by the source address register; and

a state machine, coupled to the memory, the source address register, the destination address register, and the translation circuit, the state machine configured and arranged to supply a block of platform-independent program code stored in the memory to the translation circuit and store in the memory a block of corresponding native program code output from the translation circuit.

20. The computer system of claim 19, further comprising a vector table and an object table, the object table including a plurality of entries, each entry including at least one native instruction corresponding to one of the platform-independent instructions, and the vector table including a plurality of vectors indexed by the platform-independent instructions, each vector pointing to one of the entries in the object table.

21. The computer system of claim 20, wherein entries in the object table include end codes delimiting the end of the entries, and wherein the state machine is configured and arranged to detect the end codes to terminate translation of each platform-independent instruction.

22. The computer system of claim 21, wherein selected entries in the object table further include immediate codes indicating embedded data in the block of platform-independent program code, and wherein the state machine is configured and arranged to detect the immediate codes to store embedded data directly in the corresponding block of native program code.

23. The computer system of claim 21, wherein the processor and the translation circuit are disposed on the same integrated circuit chip.

24. The computer system of claim 20, wherein the vector and object tables are stored in the memory.

25. The computer system of claim 19, wherein the platform-independent instruction comprises a Java-type bytecode.

26. The computer system of claim 19, wherein the translation circuit outputs an exception signal to the processor when a platform-independent instruction received by the translation circuit cannot be directly translated to a native instruction.

27. A method of executing program code in a format having platform-independent instructions on a processor which executes program code in a format having native instructions, the method comprising:

receiving a platform-independent instruction, including receiving a block of platform-independent program code;

storing a source address of a platform independent instruction from the block of platform-independent program code in a source address register;

translating the block of platform independent program code with a hardware-implemented translation circuit into a block of corresponding native program code including at least one corresponding native instruction using an object table including a plurality of entries, each entry matching a platform-independent instruction with at least one native instruction for the processor; and

storing the block of corresponding native program code in the memory starting at a destination address stored in a destination address register.

28. The method of claim 27, wherein translating the platform-independent instruction includes using the platform-independent instruction as an index to a vector table coupled to the object table, the vector table including a plurality of vectors, each of which points to an entry in the object table.

29. The method of claim 27, wherein the platform-independent instruction is a Java bytecode.