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High-speed, parallel, processor architecture for front-end electronics, based on a single type of ASIC, and method use thereof

  • US 5,937,202 A
  • Filed: 02/15/1996
  • Issued: 08/10/1999
  • Est. Priority Date: 02/11/1993
  • Status: Expired due to Term
First Claim
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1. A processor complex for processing data from at least one input, comprising:

  • at least a first and second processor, each having a data input and a data output, a data input of the second processor receiving data from the data output of the first processor;

    each processor being programmed with a respective algorithm for processing data received from a respective data input;

    said first processor being configured to receive raw data and process the raw data according to the respective algorithm programmed therein, and configured to receive other raw data and pass said other raw data to said second processor; and

    said second processor being configured to receive said other raw data passed from said first processor and process the other raw data according to the algorithm programmed in said second processor, and said second processor is configured to receive processed data from said first processor and pass the processed data from the data input to the data output of said second processor.

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