Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls

• US 5,937,299 A
• Filed: 04/21/1997
• Issued: 08/10/1999
• Est. Priority Date: 04/21/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Wristers, Derick J., Hause, Frederick N., Gardner, Mark I., Fulford, H. Jim Jr., Moore, Bradley T.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/837,522
• Time in Patent Office: 841 Days
• Field of Search: 438/299, 438/305, 438/585, 438/592, 438/300, 438/527, 438/529, 438/530, 438/301, 438/306, 438/307
• US Class Current: 438/299
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

An IGFET with source and drain contacts in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, forming a source and a drain that extend into the substrate, depositing a contact material over the gate, source and drain, and forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain. The gate is separated from the source and drain contacts due to a retrograde slope of the gate sidewalls, and the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material. Preferably, the contact material is a refractory metal, and the contacts are formed by converting the refractory metal into a silicide. In this manner, a highly miniaturized IGFET can be provided with densely-packed gate, source and drain contacts without the need for sidewall spacers adjacent to the gate.

Claims

1. A method of forming an IGFET, comprising the steps of:

forming a gate over a semiconductor substrate, wherein the gate includes a top surface, a bottom surface and opposing sidewalls, and the top surface has a substantially greater length than the bottom surface;

forming a source and a drain that extend into the substrate by implanting first and second dopant ions therein, wherein the top surface forms a mask preventing the source and drain regions form extending to a position proximate to the bottom surface;

annealing the substrate thereby forming a lightly doped source region extending from the source to a position proximate the bottom surface and forming a lightly doped drain region extending from the drain to a position proximate the bottom surface;

depositing a contact material over the gate, source and drain; and

forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain, wherein the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material.

2. The method of claim 1, wherein the source and drain are entirely within the substrate, and the source and drain contacts are adjacent to the substrate.

3. The method of claim 1, wherein the source and drain include elevated source and drain regions that extend above the substrate and underlying source and drain regions in the substrate, and the source and drain contacts are adjacent to the elevated source and drain regions and spaced from the substrate.

4. The method of claim 1, wherein the sidewalls of the gate are covered with a liner insulator during deposition of the contact material.

5. The method of claim 1, wherein depositing the contact material forms the gate, source and drain contacts.

6. The method of claim 5, wherein the contact material is a refractory metal, and forming the gate, source and drain contacts includes converting the refractory metal into a silicide.

7. The method of claim 1, wherein sidewalls of the source and drain contacts are substantially aligned with edges where the sidewalls of the gate intersect the top surface of the gate.

8. The method of claim 1, wherein the gate is separated from the source and drain contacts due to a retrograde slope of the sidewalls of the gate.

9. The method of claim 1, wherein the first and second dopant ions are arsenic and phosphorous.

10. A method of forming an IGFET, comprising the steps of:

providing a semiconductor substrate;

forming a gate insulator on the substrate;

forming a gate on the gate insulator, wherein the gate includes a top surface, a bottom surface and opposing sidewalls between the top and bottom surfaces, the top surface has a substantially greater length than the bottom surface, and portions of the sidewalls intersect the bottom surface and slope outward as a height of the gate increases;

forming a source and a drain that extend into the substrate by implanting first and second dopant ions in the substrate;

annealing the substrate forming lightly doped source/drain region under outward sloping sidewalls;

depositing a contact material over the gate, source and drain; and

forming a gate contact on the gate, a source contact on the source, and a drain contact on the drain, wherein the gate contact is separated from the source and drain contacts due to a lack of step coverage in the contact material, and the gate is separated from the source and drain contacts due to the retrograde slope of the sidewalls.

11. The method of claim 10, wherein the source and drain are entirely within the substrate, and the source and drain contacts are adjacent to the substrate.

12. The method of claim 10, wherein the source and drain include elevated source and drain regions above the substrate and on underlying source and drain regions in the substrate, and the source and drain contacts are adjacent to the elevated source and drain regions and spaced from the substrate.

13. The method of claim 12, wherein forming the gate and the source and drain includes depositing an epitaxial silicon layer over the substrate to form an upper gate level of the gate and the elevated source and drain regions, such that the upper gate level is separated from the elevated source and drain regions due to a lack of step coverage in the epitaxial silicon layer.

14. The method of claim 10, wherein depositing the contact material forms the gate, source and drain contacts.

15. The method of claim 10, wherein the contact material is a refractory metal, and forming the gate, source and drain contacts includes converting the refractory metal into a silicide.

16. The method of claim 10, wherein the sidewalls are exposed during deposition of the contact material.

17. The method of claim 10, wherein the sidewalls are covered with a liner insulator during deposition of the contact material.

18. The method of claim 10, wherein the first and second dopants are arsenic and phosphorous ions.

19. A method of forming an IGFET, comprising the steps of:

providing a semiconductor substrate of first conductivity type;

forming a gate oxide on the substrate;

forming a polysilicon layer on the gate oxide;

forming a masking layer over the polysilicon layer;

applying a dry etch that removes portions of the polysilicon layer beneath openings in the masking layer and portions of the polysilicon layer beneath the masking layer, wherein an unetched portion of the polysilicon layer forms a gate that includes a top surface, a bottom surface and opposing sidewalls, the top surface has a length that is substantially greater than that of the bottom surface, and the sidewalls of the gate have a retrograde slope that extends outward as a height of the gate increases;

forming a source and a drain entirely within the substrate, including implanting first and second dopants of a second conductivity type into the substrate using the gate as an implant mask for an underlying region of the substrate;

annealing the substrate to form a lightly doped regions under the retrograde slope of the gate;

depositing a refractory metal layer over the gate and regions of the source and drain to simultaneously form refractory metal segments over the gate, source and drain, wherein sidewalls of the refractory metal segments over the source and drain are substantially aligned with sidewalls of the refractory metal segment over the gate, the refractory metal segments over the source and drain are spaced from the gate due to the retrograde slope of the sidewalls of the gate, and the refractory metal segments over the source and drain are separated from the refractory metal segment over the gate due to a lack of step coverage in the refractory metal layer; and

applying a thermal cycle to convert the refractory metal segments into silicide contacts on the gate, source and drain.

20. A method of forming an IGFET, comprising the steps of:

providing a semiconductor substrate of first conductivity type;

forming a gate oxide on the substrate;

forming a polysilicon layer on the gate oxide;

forming a masking layer over the polysilicon layer;

applying a dry etch that removes portions of the polysilicon layer beneath openings in the masking layer and portions of the polysilicon layer beneath the masking layer, wherein an unetched portion of the polysilicon layer forms a lower gate level that includes a top surface, a bottom surface and opposing sidewalls, the top surface has a length that is substantially greater than that of the bottom surface, and the sidewalls of the lower gate level have a retrograde slope that extends outward as a height of the lower gate level increases;

removing regions of the gate insulator outside the lower gate level;

depositing an epitaxial silicon layer on the lower gate level and on underlying source and drain regions of the substrate to simultaneously form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region, wherein the lower gate level is at least twice as thick as the epitaxial silicon layer, sidewalls of the elevated source and drain regions are beneath and substantially aligned with opposing sidewalls of the upper gate level, the elevated source and drain regions are spaced from the lower gate level due to the retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the epitaxial silicon layer;

implanting a first and a second dopant of second conductivity type into the elevated source and drain regions, thereby doping the elevated source and drain regions as heavily doped source and drain regions;

diffusing dopant from the elevated source and drain regions into the underlying source and drain regions, thereby doping the underlying source and drain regions as lightly doped source and drain regions and converting the underlying source and drain regions from first conductivity type into second conductivity type;

depositing a refractory metal layer over the gate and the elevated source and drain regions to simultaneously form refractory metal segments over the gate, source and drain, wherein sidewalls of the refractory metal segments over the source and drain are substantially aligned with sidewalls of the refractory metal segment over the gate, the refractory metal segments over the source and drain are spaced from the gate due to the retrograde slope of the sidewalls of the lower gate level, and the refractory metal segments over the source and drain are separated from the refractory metal segment over the gate due to a lack of step coverage in the refractory metal layer; and

applying a thermal cycle to convert the refractory metal segments into suicide contacts on the gate, source and drain.