Single-etch stop process for the manufacture of silicon-on-insulator wafers

• US 5,937,312 A
• Filed: 01/11/1996
• Issued: 08/10/1999
• Est. Priority Date: 03/23/1995
• Status: Expired due to Fees

• Current Assignee: Sibond LLC
• Original Assignee: Sibond LLC
• Inventors: Iyer, Subramanian S., Craven, Robert A., Mastroianni, Mark L., Baran, Emil
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/584,058
• Time in Patent Office: 1,307 Days
• Field of Search: 438/455, 438/459, 438/406, 438/977, 148/DIG. 12
• US Class Current: 438/459
• CPC Class Codes: H01L 21/3226 of silicon on insulator
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A single-etch stop process for the manufacture of silicon-on-insulator wafers. The process includes forming a silicon-on-insulator bonded wafers comprising a substrate layer, an oxide layer, a device layer, and a device wafer. The device layer is situated between the device wafer and the oxide layer and the oxide layer is between the device layer and the substrate layer. The device wafer has a p⁺ or n⁺ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm. A portion of the device wafer is removed from the silicon-on-insulator bonded wafers and the remaining portion of the device wafer has a defect-free surface after such removal. The remaining portion of the device wafer is then etched to expose the device layer.

Claims

1. A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a p+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,

removing a portion of the device wafer from the silicon-on-insulator bonded wafer, the remaining portion of the device wafer having a defect-free surface after removal, and

immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the device wafer to expose the device layer.

2. The process of claim 1 wherein the device layer has a thickness ranging between about 0.5 and 50 μ

m.

3. The process of claim 1 wherein the device wafer has a boron concentration of at least about 1×

10¹⁷ boron atoms/cm³.

4. The process of claim 1 wherein after a portion of the device wafer is removed, the remaining portion of the device wafer has a total thickness variation of less than about 10 μ

m.

5. The process of claim 1 further comprising polishing the exposed device layer to produce a polished silicon-on-insulator wafer.

6. The process of claim 5 wherein the polished silicon-on-insulator wafer has a total thickness variation which does not exceed 10% of the maximum thickness of the device layer.

7. The process of claim 5 wherein no more than about 1 μ

m of silicon are removed when the exposed device layer is polished.

8. The process of claim 1 wherein the step of removing a portion of the device wafer comprises a coarse material removal stage followed by a smooth grinding stage.

9. The process of claim 8 wherein the coarse material removal stage comprises chemically etching or grinding.

10. The process of claim 8 wherein the step of removing a portion of the device wafer further comprises polishing the surface of the device wafer after the smooth grinding stage.

11. The process of claim 1 wherein the step of etching the remaining portion of the device wafer comprises

immersing the silicon-on-insulator bonded wafer in a bath containing hydrofluoric acid and nitric acid and further containing acetic acid or phosphoric acid, and

reconditioning the bath by adding peroxide, ozone or other reconditioning agent to the bath.

12. The process of claim 1 wherein the step of etching the remaining portion of the device wafer comprises

immersing the silicon-on-insulator bonded wafer in a bath containing hydrofluoric acid and nitric acid and further containing acetic acid or phosphoric acid, and

after the etch rate begins to diminish, withdrawing the silicon-on-insulator bonded wafer from the bath, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded wafer in the bath.

13. The process of claim 12 wherein the device wafer surface is reactivated by being immersed in water or by being exposed to air or other oxidizing atmosphere or fluid.

14. The process of claim 12 wherein the steps of reactivating the device wafer surface and reimmersing the silicon-on-insulator bonded wafer in the bath containing hydrofluoric acid, nitric acid and acetic acid are repeated at least twice.

15. The process of claim 14 wherein the device wafer surface is reactivated by being immersed in water or by being exposed to air or other oxidizing atmosphere or fluid.

16. The process of claim 14 wherein the surface is reactivated by immersing the surface in water, the water containing ozone.

17. The process of claim 1 wherein the exposed device layer is polished using a colloidal silica slurry.

18. The process of claim 1 wherein after a portion of the device wafer is removed, the thickness of the device wafer ranges from about 1 μ

m to about 50 μ

m.

19. The process of claim 1 further comprising subjecting the silicon-on-insulator bonded wafer to a high temperature annealing step after the remaining portion of the device wafer is etched.

20. The process of claim 1 further comprising edge trimming the device layer.

33. The process of claim 1 wherein after a portion of the device wafer is removed, the surface of the remaining portion of the device wafer has an average roughness of less than about 10 angstroms as determined over an area of 1 mm² with an optical interferometer.

21. A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having an n+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,

removing a portion of the device wafer from the silicon-on-insulator bonded wafer, the remaining portion of the device wafer having a defect-free surface after removal, and

immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the device wafer to expose the device layer.

22. The process of claim 21 further comprising polishing the exposed device layer to produce a polished silicon-on-insulator wafer.

23. The process of claim 22 wherein the polished silicon-on-insulator wafer has a total thickness variation which does not exceed 10% of the maximum thickness of the device layer.

24. The process of claim 22 wherein no more than about 1 μ

m of silicon are removed when the exposed device layer is polished.

25. The process of claim 21 wherein the exposed device layer is polished using a colloidal silica slurry.

26. The process of claim 21 wherein after a portion of the device wafer is removed, the thickness of the device wafer ranges from about 1 μ

m to about 50 μ

m.

27. The process of claim 21 further comprising subjecting the silicon-on-insulator bonded wafer to a high temperature annealing step after the remaining portion of the device wafer is etched.

28. The process of claim 21 further comprising edge trimming the device layer.

36. The process of claim 21 wherein after a portion of the device wafer is removed, the surface of the remaining portion of the device wafer has an average roughness of less than about 10 angstroms as determined over an area of 1 mm² with an optical interferometer.

29. A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and having a thickness ranging between about 0.5 μ

m and 50 μ

m, the oxide layer being between the device layer and the substrate layer, the device wafer having a p+ or n+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,

removing a portion of the device wafer from the silicon-on-insulator bonded wafer, the remaining portion of the device wafer having, after removal, a defect-free surface and a total thickness variation of less than about 10 μ

m,

immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the device wafer to expose the device layer,

reactivating the device wafer surface, and

polishing the exposed device layer to produce a polished silicon-on-insulator wafer.

37. The process of claim 29 wherein after a portion of the device wafer is removed, the surface of the remaining portion of the device wafer has an average roughness of less than about 10 angstroms as determined over an area of 1 mm² with an optical interferometer.

30. A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a p⁺ or n⁺ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,

removing a portion of the device wafer from the silicon-on-insulator bonded wafer,

immersing the remaining portion of the device wafer in an etchant containing hydrofluoric acid and nitric acid and further containing acetic acid or phosphoric acid, and

after the etch rate of the device wafer begins to diminish, withdrawing the silicon-on-insulator bonded wafer from the etchant, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded wafer in the etchant.

31. A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a p+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,

removing a substantial portion of the device wafer from the silicon-on-insulator bonded wafer by rough grinding,

removing a portion of the rough ground device wafer from the silicon-on-insulator bonded wafer by fine grinding,

removing a portion of the fine ground device wafer from the silicon-on-insulator bonded wafer by polishing, the remaining portion of the device wafer having a defect-free surface after removal, and

immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the polished device wafer to expose the device layer.

32. The process of claim 31 wherein after the fine grinding the surface of the remaining portion of the device wafer has an average roughness of less than about 0.1 μ

m as determined over an area of 1 cm² with a profilometer.

34. The process of claim 31 wherein after the fine grinding the surface of the remaining portion of the device wafer has an average roughness of less than about 0.02 μ

m as determined over an area of 1 cm² with a profilometer.

35. A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a n+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,

removing a substantial portion of the device wafer from the silicon-on-insulator bonded wafer by rough grinding,

removing a portion of the rough ground device wafer from the silicon-on-insulator bonded wafer by fine grinding,

removing a portion of the fine ground device wafer from the silicon-on-insulator bonded wafer by polishing, the remaining portion of the device wafer having a defect-free surface after removal, and

immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the polished device wafer to expose the device layer.

38. The process of claim 35 wherein after the fine grinding the surface of the remaining portion of the device wafer has an average roughness of less than about 0.1 μ

m as determined over an area of 1 cm² with a profilometer.

39. The process of claim 35 wherein after the fine grinding the surface of the remaining portion of the device wafer has an average roughness of less than about 0.02 μ

m as determined over an area of 1 cm² with a profilometer.