Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching

• US 5,937,319 A
• Filed: 10/31/1997
• Issued: 08/10/1999
• Est. Priority Date: 10/31/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lin, Ming-Ren, Xiang, Qi, Gupta, Subash
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/961,828
• Time in Patent Office: 648 Days
• Field of Search: 438/197, 438/230, 438/303, 438/585, 438/595, 438/596, 438/647, 438/649, 438/655, 438/656, 438/657, 438/682, 438/684, 438/721, 438/745, 438/755, 438/947, 438/FOR 351 , 438/FOR 353, 257/412, 748/DIG. 19, 748/DIG. 147
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Abstract

A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysilicon in the polysilicon gate 8 to form a metal silicide sidewall 20, and removing the metal silicide sidewall 20 by etching.

Claims

1. A method of fabricating a polysilicon gate of a metal oxide semiconductor (MOS) transistor, comprising the steps of:

(a) providing a polysilicon gate on a gate oxide layer, the polysilicon gate having a top and a sidewall;

(b) forming a conformal layer of a metal on the polysilicon gate and the gate oxide layer;

(c) removing a portion of the conformal layer to leave a spacer layer of the metal on the sidewall of the polysilicon gate;

(d) forming a metal silicide sidewall surrounding the polysilicon gate by silicidizing the metal spacer layer with the polysilicon; and

(e) removing the metal silicide sidewall from the polysilicon gate, thereby reducing the size of the polysilicon gate.

2. The method of claim 1, wherein the metal comprises cobalt (Co).

3. The method of claim 2, wherein the metal silicide comprises cobalt disilicide (CoSi₂).

4. The method of claim 1, wherein the metal comprises nickel (Ni).

5. The method of claim 1, wherein the metal comprises titanium (Ti).

6. The method of claim 1, wherein the metal comprises chromium (Cr).

7. The method of claim 1, wherein the metal comprises molybdenum (Mo).

8. The method of claim 1, further comprising providing a cap layer on the top of the polysilicon gate prior to the depositing of the conformal layer.

9. The method of claim 8, wherein the cap layer comprises silicon nitride oxide (SiON).

10. The method of claim 8, wherein the forming of the conformal layer further includes depositing the metal on the cap layer.

11. The method of claim 8, further comprising removing the cap layer subsequent to the silicidizing of the metal spacer layer.

12. The method of claim 1, wherein the removing of the metal silicide sidewall includes etching the metal silicide sidewall.

13. The method of claim 12, wherein the metal silicide sidewall is etched with a selective wet etch.

14. The method of claim 13, wherein the selective wet etch comprises hydrochloric acid (HCl).

15. The method of claim 14, wherein the selective wet etch comprises boiling concentrated HCl.

16. The method of claim 1, wherein the removing of the portion of the conformal layer comprises reactive ion etching (RIE) the conformal layer.

17. The method of claim 16, wherein the RIE of the conformal layer comprises RIE with an anisotropic etch.

18. The method of claim 1, wherein the metal spacer layer is silicidized at a temperature of about 600°

C.

19. The method of claim 1, wherein the providing of the polysilicon gate includes patterning and etching a polysilicon layer on the gate oxide layer.

20. The method of claim 1, wherein the gate oxide layer comprises silicon dioxide (SiO₂).

21. A method of fabricating a polysilicon gate of a metal oxide semiconductor (MOS) transistor, comprising the steps of:

(a) patterning and etching a polysilicon layer on a gate oxide layer to form a polysilicon gate having a top and a sidewall;

(b) providing a cap layer on the top of the polysilicon gate;

(c) depositing a conformal layer of a metal on the polysilicon gate, the gate oxide layer and the cap layer;

(d) etching the conformal layer to leave a spacer layer of the metal on the sidewall of the polysilicon gate;

(e) silicidizing the metal spacer layer with the polysilicon to form a metal silicide sidewall surrounding the polysilicon gate;

(f) removing the cap layer; and

(g) etching the metal silicide sidewall to remove the metal silicide from the polysilicon gate, thereby reducing the size of the polysilicon gate.

22. The method of claim 21, wherein the metal comprises cobalt (Co).

23. The method of claim 22, wherein the metal silicide comprises cobalt disilicide (CoSi₂).

24. The method of claim 21, wherein the metal comprises nickel (Ni).

25. The method of claim 21, wherein the metal comprises titanium (Ti).

26. The method of claim 21, wherein the metal comprises chromium (Cr).

27. The method of claim 21, wherein the metal comprises molybdenum (Mo).

28. The method of claim 21, wherein the metal silicide sidewall is etched with a selective wet etch.

29. The method of claim 28, wherein the selective wet etch comprises hydrochloric acid (HCl).

30. The method of claim 29, wherein the selective wet etch comprises boiling concentrated HCl.

31. The method of claim 21, wherein the etching of the conformal layer comprises reactive ion etching (RIE).

32. The method of claim 31, wherein the etching of the conformal layer comprises RIE with an anisotropic etch using the cap layer as an etch stop.

33. The method of claim 21, wherein the metal spacer layer is silicidized at a temperature of about 600°

C.

34. The method of claim 21, wherein the cap layer comprises silicon nitride oxide (SiON).

35. A method of fabricating a polysilicon gate of a metal oxide semiconductor (MOS) transistor, comprising the steps of:

(a) patterning and etching a polysilicon layer on a gate oxide layer to form a polysilicon gate having a top and a sidewall;

(b) depositing a conformal layer of cobalt (Co) on the polysilicon gate and the gate oxide layer;

(c) etching the conformal layer to leave a spacer layer of Co on the sidewall of the polysilicon gate;

(d) silicidizing the Co spacer layer with the polysilicon at a low silicidation temperature to form a cobalt disilicide (CoSi₂) sidewall surrounding the polysilicon gate; and

(e) etching the CoSi₂ sidewall to remove the CoSi₂ from the polysilicon gate, thereby reducing the size of the polysilicon gate.

36. The method of claim 35, further comprising providing a cap layer on the top of the polysilicon gate prior to the depositing of the conformal layer.

37. The method of claim 36, wherein the cap layer comprises silicon nitride oxide (SiON).

38. The method of claim 36, wherein the depositing of the conformal layer further includes depositing the Co on the cap layer.

39. The method of claim 36, further comprising removing the cap layer subsequent to the silicidizing of the Co spacer layer.

40. The method of claim 35, wherein the CoSi₂ sidewall is etched with a selective wet etch.

41. The method of claim 40, wherein the selective wet etch comprises hydrochloric acid (HCl).

42. The method of claim 41, wherein the selective wet etch comprises boiling concentrated HCl.

43. The method of claim 35, wherein the etching of the conformal layer comprises reactive ion etching (RIE).

44. The method of claim 43, wherein the etching of the conformal layer comprises RIE with an anisotropic etch.

45. The method of claim 35, wherein the low silicidation temperature is about 600°

C.

46. A method of fabricating a polysilicon gate of a metal oxide semiconductor (MOS) transistor, comprising the steps of:

(a) patterning and etching a polysilicon layer on a gate oxide layer to form a polysilicon gate having a top and a sidewall;

(b) providing a silicon nitride oxide (SiON) cap layer on the top of the polysilicon gate;

(c) depositing a conformal layer of cobalt (Co) on the polysilicon gate, the gate oxide layer and the SiON cap layer;

(d) etching the conformal layer to leave a spacer layer of Co on the sidewall of the polysilicon gate;

(e) silicidizing the Co spacer layer with the polysilicon at a low silicidation temperature to form a cobalt disilicide (CoSi₂) sidewall surrounding the polysilicon gate;

(f) removing the SiON cap layer; and

(g) etching the CoSi₂ sidewall to remove the CoSi₂ from the polysilicon gate, thereby reducing the size of the polysilicon gate.

47. The method of claim 46, wherein the CoSi₂ sidewall is etched with a selective wet etch.

48. The method of claim 47, wherein the selective wet etch comprises hydrochloric acid (HCl).

49. The method of claim 48, wherein the selective wet etch comprises boiling concentrated HCl.

50. The method of claim 46, wherein the etching of the conformal layer comprises reactive ion etching (RIE).

51. The method of claim 50, wherein the etching of the conformal layer comprises RIE with an anisotropic etch using the SiON cap layer as an etch stop.

52. The method of claim 46, wherein the low silicidation temperature is about 600°

C.

53. A method of fabricating a polysilicon gate of a metal oxide semiconductor (MOS) transistor, comprising the steps of:

(a) patterning and etching a polysilicon layer on a gate oxide layer to form a polysilicon gate having a top and a sidewall;

(b) depositing a conformal layer of cobalt (Co) on the polysilicon gate and the gate oxide layer by chemical vapor deposition (CVD);

(c) reactive ion etching the conformal layer with an anisotropic etch to leave a spacer layer of Co on the sidewall of the polysilicon gate;

(d) silicidizing the Co spacer layer with the polysilicon at a temperature of about 600°

C. to form a cobalt disilicide (CoSi₂) sidewall surrounding the polysilicon gate; and

(e) etching the CoSi₂ sidewall with hydrochloric acid (HCl) to remove the CoSi₂ from the polysilicon gate, thereby reducing the size of the polysilicon gate.

54. The method of claim 53, further comprising providing a cap layer on the top of the polysilicon gate prior to the depositing of the conformal layer.

55. The method of claim 54, wherein the cap layer comprises silicon nitride oxide (SiON).

56. The method of claim 54, wherein the depositing of the conformal layer further includes depositing the Co on the cap layer.

57. The method of claim 54, further comprising etching the cap layer with sulfuric acid (H₂ SO₄) to remove the cap layer from the polysilicon gate subsequent to the silicidizing of the Co spacer layer.

58. A method of fabricating a polysilicon gate of a metal oxide semiconductor (MOS) transistor, comprising the steps of:

(a) patterning and etching a polysilicon layer on a gate oxide layer to form a polysilicon gate having a top and a sidewall;

(b) providing a silicon nitride oxide (SiON) cap layer on the top of the polysilicon gate;

(c) depositing a conformal layer of cobalt (Co) on the polysilicon gate, the gate oxide layer and the SiON cap layer by chemical vapor deposition (CVD);

(d) reactive ion etching the conformal layer with an anisotropic etch using the SiON cap layer as an etch stop to leave a spacer layer of Co on the sidewall of the polysilicon gate;

(e) silicidizing the Co spacer layer with the polysilicon at a temperature of about 600°

C. to form a cobalt disilicide (CoSi₂) sidewall surrounding the polysilicon gate;

(f) etching the SiON cap layer with sulfuric acid (H₂ SO₄) to remove the SiON cap layer from the polysilicon gate; and

(g) etching the CoSi₂ sidewall with boiling concentrated hydrochloric acid (HCl) to remove the CoSi₂ from the polysilicon gate, thereby reducing the size of the polysilicon gate.