Semiconductor manufacturing process with oxide film formed on an uneven surface pattern

• US 5,937,322 A
• Filed: 07/14/1998
• Issued: 08/10/1999
• Est. Priority Date: 09/21/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Matsuura, Masazumi
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): NGUYEN, THANH T
• Application Number:
  US09/114,854
• Time in Patent Office: 392 Days
• Field of Search: 438/622, 438/623-626, 438/761, 438/780, 438/787-790, 438/253, 438/256, 438/257, 438/329, 438/396, 438/399
• US Class Current: 438/622
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

A silicon oxide film is formed on a wire array by CVD employing a gas mixture composed of a gas containing silicon atoms and hydrogen peroxide, and the thickness of the silicon oxide film in the region apart from the wire array is formed to be at least 50% of the wire thickness. Planarization of the silicon oxide film over the wire array region is attained.

Claims

1. A process for manufacturing a semiconductor device comprising:

forming a plurality of wires having a prescribed thickness on a first region of a semiconductor substrate; and

forming a silicon oxide film on said first region of said semiconductor substrate, on a second region of said semiconductor substrate surrounding said first region and on a third region of said semiconductor substrate surrounding said second region by chemical vapor deposition employing a gas mixture composed of a silicon atom containing gas and hydrogen peroxide, a thickness of said silicon oxide film becoming smaller in said second region in proportion to a distance from said first region, said silicon oxide film being planarized in said third region and a thickness of said silicon oxide film in said third region being at least 50% of but no more than said thickness of said wires.

2. A process for manufacturing a semiconductor device as recited in claim 1, wherein:

said gas mixture is composed of silane and hydrogen peroxide.

3. A process for manufacturing a semiconductor device as recited in claim 1, wherein:

said gas mixture is composed of disilane and hydrogen peroxide.

4. A process for manufacturing a semiconductor device as recited in claim 1, wherein:

said gas mixture is composed of an organic silicon compound which contains one of an organic group and an alkyl group, and hydrogen peroxide.

5. A process for manufacturing a semiconductor device as recited in claim 4, wherein said organic silicon compound is tetraethylorthosilicate.

6. A process for manufacturing a semiconductor device comprising:

forming an insulating layer on a semiconductor substrate;

forming a plurality of bit lines having a step thickness on a first region of said insulating layer; and

forming a first silicon oxide film on said first region of said semiconductor substrate and over said bit lines, on a second region of said semiconductor substrate surrounding said first region and on a third region of said semiconductor substrate surrounding said second region by chemical vapor deposition employing a gas mixture composed of a silicon atom containing gas and hydrogen peroxide;

a thickness of said first silicon oxide film becoming smaller in said second region in proportion to a distance from said first region, said first silicon oxide film being planarized in said third region and a thickness of said first silicon oxide film in said third region being at least 50% of but no more than said thickness.

7. A process for manufacturing a semiconductor device as recited in claim 6, comprising:

forming a plurality of capacitors each having an uneven cell plate with a step height on said first silicon oxide film in said first region of said semiconductor substrate; and

forming a second silicon oxide film over said capacitors and over said first, second and third regions of said semiconductor substrate by chemical vapor deposition employing said gas mixture;

a thickness of said second silicon oxide film becoming smaller in said second region in proportion to said distance from said first region, said second silicon oxide film being planarized in said third region and a thickness of said second silicon oxide film in said third region being at least 50% of but no more than said step height.

8. A process for manufacturing a semiconductor device as recited in claim 7, comprising:

forming a plurality of wires having a thickness on said second silicon oxide film in said first region of said semiconductor substrate; and

forming a third silicon oxide film over said wires and over said first, second and third regions of said semiconductor substrate by chemical vapor deposition employing said gas mixture;

a thickness of said third silicon oxide film becoming smaller in said second region in proportion to said distance from said first region, said third silicon oxide film being planarized in said third region and a thickness of said third silicon oxide film in said third region being at least 50% of but no more than said thickness.

9. A process for manufacturing a semiconductor device as recited in claim 8, comprising:

forming at least one of said first, second and third silicon oxide films to be at least one half of said step thickness, said step height and said thickness, respectively.

10. A process for manufacturing a semiconductor memory device on a semiconductor substrate having a memory cell region, a peripheral circuit region and a intermediate region disposed between said memory cell region and peripheral circuit region, comprising:

forming a plurality of memory cell transistors in said memory cell region and having a first step height;

forming a plurality of word lines connected to selected ones of said memory cell transistors and having a second step height;

forming a plurality of wires over said transistors having a third step height; and

forming a first silicon oxide film in said memory cell region and in said peripheral circuit region and over said plurality of wires, said first silicon oxide film having a first thickness in said memory cell region, a second thickness in said intermediate region and a third thickness in said peripheral circuit region;

wherein said first thickness is greater than said at third step height and said third thickness is at least 50% of but no more than said third step height.

11. A method as recited in claim 10, comprising:

forming a second silicon oxide film over said memory cell transistors in said memory cell region, said intermediate region and said peripheral circuit region;

said second silicon oxide film having a fourth thickness in said memory cell region, a fifth thickness in said intermediate region and a sixth thickness in said peripheral circuit region;

wherein said fourth thickness is greater than said at least one said first and second step heights and said sixth thickness is at least 50% of but no more than said at least one first and second step heights.

12. A method as recited in claim 10, comprising:

forming a plurality of cell capacitors connected to selected ones of said memory cell transistors and having a fourth step height;

forming a second silicon oxide film over said plurality of capacitors in said memory cell region, said intermediate region and said peripheral circuit region;

said second silicon oxide film having a fourth thickness in said memory cell region, a fifth thickness in said intermediate region and a sixth thickness in said peripheral circuit region;

wherein said fourth thickness is greater than said fourth step height and said sixth thickness is at least 50% of but no more than said fourth step height.

13. A method as recited in claim 11, comprising:

forming a plurality of cell capacitors connected to selected ones of said memory cell transistors and having a fourth step height;

forming a third silicon oxide film over said plurality of capacitors in said memory cell region, said intermediate region and said peripheral circuit region;

said third silicon oxide film having a seventh thickness in said memory cell region, an eighth thickness in said intermediate region and a ninth thickness in said peripheral circuit region;

wherein said seventh thickness is greater than said fourth step height and said ninth thickness is at least 50% of but no more than said fourth step height.

14. A method as recited in claim 13, comprising at least one of:

forming said first silicon oxide film to have said second thickness substantially continuously reducing from said first thickness to said third thickness;

forming said second silicon oxide films to have said fifth thickness substantially continuously reducing from said fourth thickness to said sixth thickness; and

forming said third silicon oxide film to have said eighth thickness substantially continuously reducing from said seventh thickness to said ninth thickness.

15. A method as recited in claim 14, comprising:

forming at least one said first, second and third silicon oxide films such that at least one of said third, sixth and ninth thicknesses, respectively, is substantially uniform.

16. A method as recited in claim 13, comprising:

forming at least one of said first, second and third silicon oxide films from a gas mixture composed of a silicon atom containing gas and hydrogen peroxide.

17. A method as recited in claim 11, comprising:

forming said first silicon oxide film to having a thickness in said third region approximately at least 50% of said third step height.

18. A method as recited in claim 10, comprising forming said first silicon oxide film using chemical vapor deposition employing a gas mixture composed of a silicon atom containing gas and hydrogen peroxide.

19. A method as recited in claim 11, comprising forming said second silicon oxide film using chemical vapor deposition employing a gas mixture composed of a silicon atom containing gas and hydrogen peroxide.

20. A method as recited in claim 12, comprising forming said second silicon oxide film using chemical vapor deposition employing a gas mixture composed of a silicon atom containing gas and hydrogen peroxide.