Method and apparatus for suspending the writing of a nonvolatile semiconductor memory with program suspend command

• US 5,937,424 A
• Filed: 02/27/1997
• Issued: 08/10/1999
• Est. Priority Date: 09/20/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kreifels, Jerry, Dalvi, Vishram Prakash, Rozman, Rodney R., Haid, Christopher John, Brown, Charles W., Hazen, Peter K., Bekele, Fasil G., Price, Thomas C., Leak, David A., Baker, Alan E.
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Thai, Tuan V.
• Application Number:
  US08/807,385
• Time in Patent Office: 894 Days
• Field of Search: 711/2, 711/100, 711/103, 711/154, 711/169, 711/166, 711/167, 365/185.11, 365/185.29, 365/185.33, 365/218
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it

Abstract

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Claims

1. A nonvolatile memory comprising:

a memory array;

a command register, wherein the command register comprises a resolution circuit coupled to communicate with a memory array control circuitry, the command register capable of decoding a program suspend command provided to the command register by a plurality of data inputs to the nonvolatile memory, the command register providing a suspend signal as an output; and

the memory array control circuitry coupled to receive the suspend signal from the command register, the memory array control circuitry coupled to provide control signals to the memory array to perform a program operation in which data provided to the nonvolatile memory is written to the memory array, the memory array control circuitry suspending the program operation responsive to receiving the suspend signal.

2. The nonvolatile memory of claim 1, wherein the command register further comprises:

a command decoder coupled to receive the plurality of data inputs to the nonvolatile memory, the command decoder providing a decoded program suspend signal at a command decoder output; and

a program suspend latch coupled to receive the decoded program suspend signal from the command decoder, the program suspend latch coupled to provide the suspend signal to the memory array control circuitry.

3. The nonvolatile memory of claim 2, wherein the command decoder decodes a program resume command to provide a program resume signal, and the command register further comprises:

a program resume latch coupled to receive the program resume signal from the command decoder, the program resume latch coupled to provide an input to the memory array control circuitry.

4. The nonvolatile memory of claim 3, wherein the resolution circuit controls operation of the memory array control circuitry based on commands provided to the command register by the plurality of data inputs to the nonvolatile memory and based on signals provided by the memory array control circuitry.

5. In a system comprising a processor and a nonvolatile memory coupled to the processor, wherein the nonvolatile memory comprises a command register, the command register comprising a resolution circuit coupled to communicate with memory array control circuitry, a method of reading code from the nonvolatile memory, the method comprising the steps of:

(a) suspending a first non-read operation being performed in the nonvolatile memory;

(b) suspending a second non-read operation being performed in the nonvolatile memory;

(c) providing code from the nonvolatile memory to the processor;

(d) resuming the second non-read operation; and

(e) resuming the first non-read operation.

6. The method of claim 5, further comprising the step of:

(f) executing the code by the processor.

7. The method of claim 5, wherein the first non-read operation is a program operation, during which data is written to a memory array within the nonvolatile memory.

8. The method of claim 5, wherein the first non-read operation is an erase operation, during which a block of a memory array within the nonvolatile memory is erased.

9. The method of claim 5, wherein only a suspended operation can be resumed.

10. The method of claim 5, wherein operations are resumed in the reverse order of which the operations are suspended.

11. The method of claim 5, wherein the first non-read operation is suspended and resumed a plurality of times.

12. The method of claim 5, wherein the second non-read operation is suspended and resumed a plurality of times.

13. The method of claim 5, wherein a plurality of second non-read operations is performed before resuming the suspended first non-read operation.

14. The method of claim 5, wherein one of a plurality of non-read operations is performed, suspended, and resumed after resuming and completing the suspended second non-read operation and before resuming the suspended first non-read operation.

15. The method of claim 5, wherein a plurality of non-read operations is performed, suspended, and resumed before resuming the suspended first non-read operation.

16. The method of claim 5, wherein a plurality of non-read operations is performed after resuming and completing the suspended second non-read operation.