System and method for initializing a multinode multiprocessor computer system

• US 5,938,765 A
• Filed: 08/29/1997
• Issued: 08/17/1999
• Est. Priority Date: 08/29/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: Sequent Computer Systems, Inc. (International Business Machines Corporation)
• Inventors: Gage, Robert Bruce, Perrigo, Darin Jon, Dove, Kenneth Frank
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): VO, TIM T
• Application Number:
  US08/924,038
• Time in Patent Office: 718 Days
• Field of Search: 395/651, 395/652, 395/653, 395/500, 395/311, 395/750.07, 395/700.52
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

An apparatus and method for initializing a shared-memory, multinode multiprocessor computer system. The nodes in the multiprocessor computer system separately and independently run standard PC-based BIOS routines in parallel for initialization of the nodes. These BIOS routines set addresses of hardware components on each node as though the nodes are in a single-node environment. After completion of BIOS, the addresses of the hardware components are reprogrammed to conform with the multinode environment. A master processor then takes control to boot the operating system on the multinode environment.

Claims

1. In a multiprocessor computer system having a shared memory distributed among multiple nodes, a method of initializing the computer system, the method comprising the following steps:

initializing a node using BIOS for a single-node environment so that addresses of hardware components on the node conform to a single-node memory map;

after the BIOS are complete, re-programming the addresses of the hardware components on the node to conform to a multinode memory map; and

booting an operating system that runs in conformance with the multinode memory map.

2. The method of claim 1 wherein the initializing step includes building a multiprocessor specification table that defines addresses of the hardware components on the multiprocessor computer system.

3. The method of claim 1 wherein the re-programming step includes obtaining a node identification for the node and calculating addresses conforming to the multinode memory map using the node identification.

4. The method of claim 1 wherein the re-programming step includes obtaining a node identification, an offset, and a base address and adding the base address to the product of the node identification and the offset to obtain a resultant address conforming to the multinode memory map.

5. The method of claim 1 wherein the hardware components include a PCI bridge and memory controller located on the node.

6. The method of claim 1 further including setting an initialization flag indicating that the node has completed local initialization.

7. The method of claim 1 wherein the booting step includes copying the operating system into memory on the computer system and executing the operating system.

8. The method of claim 1 wherein the initializing and reprogramming steps are applied to more than one node of the computer system.

9. A computer-readable medium on which is stored instructions for executing the steps of claim 1.

10. The method of claim 2 further including updating the multiprocessor specification table to conform with the multinode memory map.

11. The method of claim 4 further including writing the resultant address to an address control register of a hardware component on the node.

12. The method of claim 6 further including assigning one of the processors on a node in the multiprocessor computer system to read each node'"'"'s initialization flag to determine if initialization of all the nodes is complete.

13. The method of claim 12 further including building a system configuration data structure that indicates whether the nodes have completed initialization.

14. In a multiprocessor computer system having a shared memory distributed among multiple nodes, a method of initializing the computer system, the method comprising the following steps:

upon power up or restart of the computer system, running a PC-based BIOS routine independently and in parallel on each node;

upon completion of the BIOS routine, re-programming addresses of hardware components on a node to conform to a multinode memory map and setting a flag in memory indicating initialization is complete for that node;

assigning a master processor that controls booting the operating system after the BIOS on each node is complete; and

loading and executing the operating system using the master processor.

15. The method of claim 14 further including setting address registers for hardware components according to a single-node memory map.

16. The method of claim 15 further including re-programming the address registers in conformance with a multinode memory map after the PC-based BIOS are complete.

17. A multiprocessor computer system with shared memory distributed among multiple nodes, comprising:

a first node including one or more processors, a local bus and a snoopy cache protocol engine for monitoring requests on the local bus, the first node being initialized by a first BIOS routine stored locally on the first node;

a second node coupled to the first node, the second node including one or more processors, a local bus and a snoopy cache protocol engine for monitoring requests on the local bus, the second node being Initialized by a second BIOS routine stored locally on the second node and running in parallel with the first BIOS routine;

a processor on each of the first and second nodes that re-programs addresses on the nodes to conform to a multinode memory map;

a system interconnect coupling the first node to the second node; and

a master processor on one of the multiple nodes in the computer system for monitoring the first and second nodes and for booting an operating system on the multiprocessor system upon the completion of initialization of the first and second nodes by the BIOS routines on the first and second nodes.

18. The computer system of claim 17 wherein the computer system includes at least two nodes.

19. In a multiprocessor computer system having a shared memory distributed among multiple nodes, a method of initializing the computer system, the method comprising the following steps:

initializing a node to a first local address layout In conformance with a single-node memory map;

re-programming the first local address layout to conform to a multinode memory map as follows;

obtaining a node identification.;

obtaining a memory offset based on a multinode memory map;

obtaining a base address for the multinode memory map; and

calculating a second local address layout by adding the base address to the product of the node identification and the memory offset.

20. In a multiprocessor computer system having a shared memory distributed among multiple nodes, a method of initializing the computer system, the method comprising:

initializing at least two nodes in parallel using BIOS for a single-node environment so that addresses of hardware components on each node conform to a single-node memory map for the node; and

after the BIOSes are complete, re-programming the addresses of the hardware components on each node to conform to a multinode memory map for the computer system.