Linear feedback shift register, multiple input signature register, and built-in self test circuit using such registers

• US 5,938,784 A
• Filed: 10/15/1997
• Issued: 08/17/1999
• Est. Priority Date: 10/21/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Heon-Cheol
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/951,189
• Time in Patent Office: 671 Days
• Field of Search: 371/22.31, 371/22.5, 371/22.4, 371/22.33, 371/25.1, 371/27.2, 395/183.06, 395/183.18, 395/183.19, 364/489, 364/580, 324/765, 365/201, 714/25, 714/30, 714/43, 714/728, 714/733, 714/742
• US Class Current: 714/733
• CPC Class Codes: G01R 31/31813 Test pattern generators

Abstract

A built-in self test (BIST) circuit using a linear feedback shift register (LFSR) and a multiple input signature register (MISR) requiring reduced circuitry exclusive of the number of inputs and outputs of the circuit to be tested. The BIST circuit is built in a prescribed circuit having a memory to test a target circuit in the prescribed circuit. The BIST circuit includes an LFSR, including a first logic section which is composed of a plurality of XOR gates and selection sections, and a first memory which is a part of the memory, for performing a primitive polynomial, an MISR, including a second logic section which is composed of a plurality of XOR gates and selection sections, and a second memory which is a part of the memory, for performing the primitive polynomial, and a BIST control section for controlling data input/output between the first and second memories and the target circuit and providing selection signals for controlling the selection sections in the first and second logic sections, the BIST control section controlling the target circuit and comparing operation results of the target circuit to perform the test of the target circuit.

Claims

1. A built-in self test (BIST) circuit formed within a target circuit having a memory, said BIST comprising:

a linear feedback shift register (LFSR), including a first logic section having a plurality of XOR gates and selection means, and a first memory which is a part of said memory of said target circuit, for performing a primitive polynomial read out from the memory of the target circuit;

a multiple input signature register (MISR), including a second logic section which is composed of a plurality of XOR gates and selection means, and a second memory which is a part of said memory of said target circuit, for performing said primitive polynomial from the memory of the target circuit; and

a BIST control section for controlling data input/output between said first and second memories and said target circuit and providing selection signals for controlling said selection means in said first and second logic sections, said BIST control section controlling said target circuit and comparing operation results of the target circuit.

2. A built-in self test (BIST) circuit as claimed in claim 1, wherein said memory in said target circuit is shared by said LFSR and said MISR to serve as said first and second memories instead.

3. A built-in self test (BIST) circuit as claimed in claim 1, wherein said linear feedback shift register (LFSR) comprises:

a storage element for storing a coefficient of the primitive polynomial;

an XOR gate adapted to receive said coefficient and data of said primitive polynomial read out from memory of the target circuit, and outputting an XOR-gated signal responsive to said coefficient and data of said primitive polynomial; and

selection means adapted to receive said XOR-gated signal and data used in the target circuit, said selection means being operative under a selection signal to selectively output said data used in the target circuit to the memory of the target circuit in response to the selection signal.

4. A built-in self test (BIST) circuit as claimed in claim 1, wherein said multiple input signature register (MISR) comprises:

a storage element for storing a coefficient of a primitive polynomial;

an XOR gate adapted to receive said coefficient, said data of said primitive polynomial read out from memory of the target circuit and data externally inputted, and outputting an XOR-gated signal responsive to said coefficient, the data of said primitive polynomial, and the data externally inputted; and

selection means adapted to receive said XOR-gated signal, said data used in the target circuit, said selection means being operative under a selection signal to selectively output said data used in the target circuit to the memory of the target circuit in response to the selection signal.

5. A method for testing a target circuit coupled to a memory over a data bus, comprising the steps of:

coupling a test circuit to the memory associated with the target circuit, said test circuit including a plurality of storage elements;

storing a coefficient of a primitive polynomial within at least one of the storage elements;

reading out data of the primitive polynomial from the memory associated with the target circuit;

XOR-gating the coefficient of the primitive polynomial from said storage element with the data of said primitive polynomial;

generating a selection signal corresponding to either a test mode or a normal mode for controlling data input/output from said memory;

multiplexing an output of the XOR-gating step with data received over said data bus; and

selectively outputting an output of the XOR-gating step to said memory responsive to the test mode selection signal, otherwise shunting the data received over said data bus to memory.

10. The method of claim 5, further including the steps of:

generating a distinct memory address from that in normal mode; and

shunting the output from the XOR-gated step to the distinct memory address responsive to the test mode selection signal.

11. The method of claim 5, further including the steps of:

resetting an address generation logic circuit associated with the memory; and

shunting the output from the XOR-gated step to the `0` address responsive to the test mode selection signal.

6. A linear feedback shift register (LFSR) adapted to test a target circuit, said target circuit having a data bus coupled to a plurality of memory cells, the LFSR comprising:

a plurality of storage elements, each of said elements being adapted to store a respective one coefficient of a primitive polynomial resulting from a psuedo-random signal;

a plurality of exclusive-OR gates (XORs), each of said gates being adapted to generate XOR-gated values responsive to an output read out from a respective one of the plurality of storage elements and primitive polynomial data read out from the memory cells coupled to the target circuit;

a control circuit adapted to output a selection signal corresponding to either a normal mode or a test mode; and

a plurality of multiplexers (MUXs), each of said MUXs receiving a respective one of the XOR-gated values, data from the target circuit data bus, and the output selection signal generated from the control circuit, and outputting to a respective one of the memory cells either the XOR-gated value responsive to the test mode selection signal or data from said data bus responsive to the normal mode selection signal.

7. The LFSR of claim 6, further including a memory output path configured to shunt data from the one memory cell to a next XOR gate of the plurality of XORs of the LFSR to thereby form a shift chain.

8. A multiple input signature register (MISR) adapted to test a target circuit, said target circuit having a data bus coupled to a plurality of memory cells, the MISR comprising:

a plurality of storage elements, each of said elements being adapted to store a respective one coefficient of a primitive polynomial resulting from a pseudo-random signal;

a plurality of exclusive-OR gates (XORs), each of said gates being adapted to generate XOR-gated values responsive to an output read out from a respective one of the plurality of storage elements, primitive polynomial data read out from the memory cells of the target circuit, and data supplied to the plurality of gates in parallel;

a control circuit adapted to output a selection signal corresponding to either a normal mode or a test mode; and

a plurality of multiplexers (MUXs), each of said MUXs receiving a respective one of the XOR-gated values, data from the target circuit data bus, and the output selection signal generated from the control circuit, and outputting to a respective one of the memory cells the XOR-gated value responsive to the test mode selection signal and data responsive to the normal mode selection signal.

9. The MISR of claim 8, further including a memory output path configured to shunt data from the one memory cell to a next XOR gate of the plurality of XORs of the MISR to thereby form a shift chain.

12. A method for operating a test circuit with a target circuit having a memory associated therewith, the method comprising the steps of:

coupling a test circuit with memory associated with the target circuit;

reading a coefficient C_n of a primitive polynomial P=1+C₁ X¹ +C₂ X² + . . . C_n-1 X^n-1 +C_n Xⁿ into a first XOR gate;

receiving in a first multiplexer an output of the first XOR gate, data input from a data bus of the target circuit, and a selection signal having a normnal-mode state and a test-mode state;

outputting a first multiplexer signal to a first cell of the memory responsive to the selection signal;

reading out the first multiplexer signal from the first cell to a second XOR gate together with the coefficient C_n+1 ;

receiving in a second multiplexer an output of the second XOR gate and data input from the data bus of the target circuit;

outputting a second multiplexer signal to a second cell of the memory to thereby form a shift chain.