Structure and process for buried diode formation in CMOS

• US 5,939,767 A
• Filed: 03/31/1998
• Issued: 08/17/1999
• Est. Priority Date: 05/07/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H., Leidy, Robert K., Holmes, Steven J., Brown, Jeffrey S.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/052,512
• Time in Patent Office: 504 Days
• Field of Search: 257/355, 257/173, 257/106, 257/199, 257/481, 257/551, 257/603
• US Class Current: 257/551
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.

Claims

1. A buried Zener diode comprising:

a) a well region formed in a semiconductor substrate;

b) a first well edge implant, the first well edge implant formed at an edge of the well region in the semiconductor substrate, the first well edge implant abutting the edge of the well region; and

c) a second well edge implant, the second well edge implant formed at the edge of the well region in the semiconductor substrate and wherein the second well edge implant abuts the first well edge implant.

2. The buried Zener diode of claim 1 wherein the first well edge implant comprises an N+ type implant and wherein the second well edge implant comprises a P+ type implant and wherein the well region comprises an N type well region.

3. The buried Zener diode of claim 1 wherein the first well edge implant comprises a P+ type implant and wherein the second well edge implant comprises an N+ type implant and wherein the well region comprises a P type well region.

4. The buried Zener diode of claim 1 wherein the first and second edge implants are formed under a shallow trench isolation.

5. A buried Zener diode comprising:

a) a semiconductor substrate;

b) a well region formed in the semiconductor device, the well region having an edge, and

c) a plurality of well edge implants formed in the well region and the semiconductor substrate wherein at least two of the well edge implants abut each other, and wherein one of the two of the plurality of well edge implants that abut each other is formed in the well region and abuts the edge, and the other of the two of the plurality of well edge implants that abut each other is formed in the substrate.

6. The buried Zener diode of claim 5 wherein one of the two of the plurality of well edge implants that abut each other comprises an N+ type implant and the other well edge implant comprises a P+ type implant and wherein the well region comprises an N type well region.

7. The buried Zener diode of claim 5 wherein one of the two of the plurality of well edge implants that abut each other comprises a P+ type implant and the other well edge implant comprises an N+ type implant and wherein the well region comprises an P type well region.

8. The buried Zener diode of claim 5 wherein the plurality of well edge implants are formed under a shallow trench isolation.