Low consumption linear voltage regulator with high supply line rejection

• US 5,939,867 A
• Filed: 08/27/1998
• Issued: 08/17/1999
• Est. Priority Date: 08/29/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pulvirenti, Francesco, Milazzo, Patrizia, Capici, Salvatore Vincenzo
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/141,251
• Time in Patent Office: 355 Days
• Field of Search: 323/280, 323/268, 323/273, 323/277, 323/282, 323/312, 323/316
• US Class Current: 323/277
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence

Abstract

A linear type of voltage regulator, having an input terminal adapted to receive a supply voltage thereon, and an output terminal adapted to deliver a regulated output voltage, includes a power transistor and a driving circuit therefor. The driving circuit includes an operational amplifier having a differential input stage biased by a bias current which varies proportionally with the output current of the regulator.

Claims

1. A linear voltage regulator comprising:

an input terminal adapted to recieve a supply voltage thereon;

an output terminal adapted to deliver a regulated output voltage;

a power transistor having a control terminal and having a main conduction path connected in a path between the input terminal and the output terminal;

an output current sensor for sensing an output current flowing along the path between the input terminal and the output terminal;

an operational amplifier having a differential input stage biased by a bias current, and having a first input terminal connected to a voltage reference, a second input terminal coupled to the output terminal, and an output terminal coupled to the control terminal of the power transistor; and

a bias current generator cooperating with said output current sensor for generating the bias current of the differential stage to vary proportionally with a value of the output current flowing in the path between the input terminal and the output terminal.

2. A linear voltage regulator according to claim 1, wherein said output current sensor comprises a sensing resistor connected in series with the main conduction path of the power transistor.

3. A linear voltage regulator according to claim 2, wherein said bias current generator comprises a transconductance operational amplifier having first and second inputs connected to first and second terminals, respectively, of said sensing resistor to measure a difference potential thereacross, and having an output terminal delivering an output current which is proportional to the difference potential across said sensing resistor.

4. A linear voltage regulator according to claim 3, wherein the differential input stage of said operational amplifier is biased by output current from the transconductance amplifier.

5. A linear voltage regulator according to claim 1, wherein said power transistor is an N-channel MOS transistor.

6. A linear voltage regulator according to claim 1, further comprising a charge pump for supplying said operational amplifier a boosted voltage relative to the supply voltage.

7. A linear voltage regulator according to claim 1, further comprising a voltage divider coupled to the output terminal;

and wherein a first input terminal of the operational amplifier is a non-inverting input terminal, and wherein a second input terminal is an inverting input terminal coupled to the output terminal through said voltage divider.

8. A linear voltage regulator comprising:

an input terminal adapted to receive a supply voltage thereon;

an output terminal adapted to deliver a regulated output voltage;

a power transistor having a control terminal and having a main conduction path connected in a path between the input terminal and the output terminal;

a sensing resistor connected in series with the main conduction path of the power transistor for sensing an output current flowing along the path between the input terminal and the output terminal;

an operational amplifier having a differential input stage biased by a bias current, and having a first input terminal connected to a voltage reference, a second input terminal coupled to the output terminal, and an output terminal coupled to the control terminal of the power transistor; and

a transconductance operational amplifier having first and second inputs connected to first and second terminals, respectively, of said sensing resistor to measure a difference potential thereacross, and having an output terminal delivering an output current to bias the differential input stage of said operational amplifier based upon the difference potential.

9. A linear voltage regulator according to claim 8, wherein said transconductance amplifier biases the differential input stage proportional to current flow between the input terminal and the output terminal.

10. A linear voltage regulator according to claim 8, wherein said power transistor is an N-channel MOS transistor.

11. A linear voltage regulator according to claim 8, further comprising a charge pump for supplying said operational amplifier a boosted voltage relative to the supply voltage.

12. A linear voltage regulator according to claim 8, further comprising a voltage divider coupled to the output terminal;

and wherein a first input terminal of the operational amplifier is a non-inverting input terminal, and wherein a second input terminal is an inverting input terminal coupled to the output terminal through said voltage divider.

13. A linear voltage regulator comprising:

a power transistor having a control terminal and defining a main conduction path;

an operational amplifier having a differential input stage biased by a bias current, and having a first input terminal connected to a voltage reference, and an output terminal coupled to the control terminal of the power transistor; and

a bias current generator for generating the bias current of the differential stage to vary proportionally with a value of the output current flowing in the main conduction path.

14. A linear voltage regulator according to claim 13, wherein said bias current generator comprises a sensing resistor connected in series with the main conduction path of the power transistor.

15. A linear voltage regulator according to claim 14, wherein said bias current generator comprises a transconductance operational amplifier having first and second inputs connected to first and second terminals, respectively, of said sensing resistor to measure a difference potential thereacross, and having an output terminal delivering an output current which is proportional to the difference potential across said sensing resistor.

16. A linear voltage regulator according to claim 15, wherein the differential input stage of said operational amplifier is biased by output current from the transconductance amplifier.

17. A linear voltage regulator according to claim 13, wherein said power transistor is an N-channel MOS transistor.

18. A linear voltage regulator according to claim 13, further comprising a charge pump for supplying said operational amplifier a boosted voltage relative to the supply voltage.

19. A linear voltage regulator according to claim 13, further comprising a voltage divider coupled to an inverting input terminal of said operational amplifier.

20. A method for linear voltage regulation comprising the steps of:

providing a power transistor having a control terminal and defining a main conduction path;

providing an operational amplifier having a differential input stage biased by a bias current, and having a first input terminal connected to a voltage reference, and an output terminal coupled to the control terminal of the power transistor; and

generating the bias current for the differential stage to vary proportionally with a value of the output current flowing in the main conduction path.

21. A method according to claim 20, wherein the step of generating the bias current comprises connecting a sensing resistor in series with the main conduction path of the power transistor.

22. A method according to claim 21, wherein the step of generating the bias current comprises connecting a transconductance operational amplifier having first and second inputs to first and second terminals, respectively, of the sensing resistor to measure a difference potential thereacross, and having an output terminal delivering an output current which is proportional to the difference potential across the sensing resistor.

23. A method according to claim 20, wherein the power transistor is an N-channel MOS transistor;

and further comprising the step of supplying the operational amplifier a boosted voltage relative to the supply voltage.