Thin-film transistor liquid crystal display devices having high resolution

• US 5,940,059 A
• Filed: 02/28/1997
• Issued: 08/17/1999
• Est. Priority Date: 02/28/1996
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Gyu-su, Kim, Dong-gyu
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): Osorio, Ricardo
• Application Number:
  US08/808,340
• Time in Patent Office: 900 Days
• Field of Search: 345/87, 345/90-92, 345/98, 345/100
• US Class Current: 345/91
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/36 using liquid crystals

Abstract

Liquid crystal display devices include a first row of viewable liquid crystal display cells having data inputs electrically connected to a plurality of data lines (D1-Dn), control gates commonly connected to a first gate line (e.g., G1) and storage capacitors (Cst) having first electrodes electrically connected to a zeroth gate line (e.g., G0). A second row of viewable liquid crystal display cells are also provided having data inputs electrically connected to a plurality of data lines (D1-Dn), control gates commonly connected to a second gate line (e.g., G2) and storage capacitors (Cst) having first electrodes electrically connected to a first gate line (e.g., G1). Moreover, to maintain the RC delay value of the zeroth gate line at a level equal to the RC delay values associated with the higher order gate lines (e.g., G1-Gn), a row of nonviewable or "dummy" liquid crystal display cells are provided having data inputs electrically connected to the plurality of data lines, control gates commonly connected to the zeroth gate line and storage capacitors having first electrodes electrically coupled together. This row of nonviewable cells are provided to "mimic" a row of viewable cells so that the RC delay values associated with the zeroth gate line equals the RC delay value associated with the other gate lines in the array. The row of nonviewable cells may also be replaced by a variable resistance device (e.g., potentiometer, resistor ladder, etc.) and a variable capacitance device which are electrically coupled in series between the zeroth gate line and respective reference potentials (e.g., Vcom, GND, etc.). These variable devices are adjusted so that the total effective RC delay values associated with the zeroth gate line equals the RC delay value associated with the other gate lines.

Claims

1. A liquid crystal display device, comprising:

a liquid crystal display panel including;

a first row of viewable liquid crystal display cells having data inputs electrically connected to a plurality of data lines, control gates commonly connected to a first gate line and storage capacitors having first electrodes electrically connected to a zeroth gate line;

a second row of viewable liquid crystal display cells having data inputs electrically connected to the plurality of data lines, control gates commonly connected to a second gate line and storage capacitors having first electrodes electrically connected to the first gate line;

a gate line driving circuit electrically coupled to the first and second gate lines;

a variable resistance device external to said display panel and said gate line driving circuit and electrically coupled in series between the zeroth gate line and a first reference potential, and

a variable capacitance device external to said display panel and said gate line driving circuit and electrically coupled in series between the zeroth gate line and a second reference potential;

wherein said gate line driving circuit is not electrically connected to the zeroth gate line.

2. The display device of claim 1, wherein the first reference potential equals the second reference potential.

3. This display device of claim 1, wherein the zeroth gate line is not electrically connected to any control gates of display cells in said liquid crystal display panel.

4. A liquid crystal display device, comprising:

a liquid crystal display panel including;

a first row of viewable liquid crystal display cells having data inputs electrically connected to a plurality of data lines, control gates commonly connected to a first gate line and storage capacitors having first electrodes electrically connected to a zeroth gate line;

a second row of viewable liquid crystal display cells having data inputs electrically connected to the plurality of data lines, control gates commonly connected to a second gate line and storage capacitors having first electrodes electrically connected to the first gate line;

a gate line driving circuit electrically coupled to the first and second gate lines;

a variable resistance device external to said display panel and said gate line driving circuit and electrically coupled in series between the zeroth gate line and a first reference potential; and

a variable capacitance device external to said display panel and said gate line driving circuit and electrically coupled in series between the zeroth gate line and a second reference potential;

wherein the zeroth gate line is not electrically connected to any control gates of display cells in said liquid crystal display panel.