Nonvolatile semiconductor memory device

• US 5,940,321 A
• Filed: 05/30/1997
• Issued: 08/17/1999
• Est. Priority Date: 06/29/1994
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aritome, Seiichi, Takeuchi, Ken, Tanaka, Tomoharu, Sakui, Koji
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/866,350
• Time in Patent Office: 809 Days
• Field of Search: 365/185.17, 365/185.05, 365/185.12, 365/185.23, 365/185.24, 365/185.11, 365/230.03, 365/185.18, 365/189.01
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A nonvolatile semiconductor memory device comprises a memory cell array in which a plurality of memory cell units are arranged in a matrix, and a first and second common signal lines for exchanging signals with the memory cell array, wherein each of the memory cell units contains a nonvolatile memory section having at least one nonvolatile memory cell, a first select MOS transistor for making the nonvolatile memory section conducting to the first common signal line, and a second select MOS transistor with a threshold voltage different from that of the first select MOS transistor for making the nonvolatile memory section conducting to the second common signal line.

Claims

1. A nonvolatile semiconductor memory device comprising:

a first and second common signal lines;

at least one word line; and

a memory cell array in which a plurality of memory cell units arranged in a matrix, each of said plurality of memory cell units containing a memory cell section having at least one nonvolatile memory cell and having a first end and a second end;

wherein

at said first end of each of said plurality of memory cell units, a plurality of memory cell units sharing said at least one word line share a contact and are connected to said first common signal line; and

at said second end of each of said plurality of memory cell units, a plurality of memory cell units sharing said at least one word line share a contact and are connected to said second common signal line.

2. A nonvolatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cell units contains at least one select MOS transistor for making said memory cell section conducting to at least one of said first and second common signal lines.

6. A nonvolatile semiconductor memory device according to claim 1, further comprising means for biasing said first common signal line, to which said first end of each of said plurality of memory cell units is connected, to a read potential and keeping said second common signal line, to which said second end of each of said plurality of memory cell units is connected, at a read unselected potential in reading the data in at least one of said plurality of memory cell units.

7. A nonvolatile semiconductor memory device according to claim 2, further comprising means for biasing said first common signal line, to which said first end of each of said plurality of memory cell units is connected, to a read potential and keeping said second common signal line, to which said second end of each of said plurality of memory cell units, at a read unselected potential in reading the data in at least one of said plurality of memory cell units.

11. A nonvolatile semiconductor memory device according to claim 1, further comprising means for biasing said first common signal line, to which said first end of each of said plurality of memory cell units is connected, to a "1" program potential or a "0" program potential according to the programming data and keeping said second common signal line, to which said second end of each of said plurality of memory cell units is connected, at a program unselected potential in programming the data in at least one of said plurality of memory cell units.

12. A nonvolatile semiconductor memory device according to claim 2, further comprising means for biasing said first common signal line, to which said first, end of each of said plurality of memory cell units is connected, to a "1" program potential or a "0" program potential according to the programming data and keeping said second common signal line, to which said second end of each of said plurality of memory cell units is connected, at a program unselected potential in programming the data in at least one of said plurality of memory cell units.

16. A nonvolatile semiconductor memory device according to claim 2, in which said plurality of memory cell units constitute a plurality of memory blocks each having a select gate, further comprising means for applying an unselected gate voltage to the select gate in an unselected block so that the select MOS transistors in the plurality of memory cell units in said unselected block not to be read from or written into may turn off, in reading and programming the data from and into at least one of said plurality of memory cell units.

20. A nonvolatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cell units contains a first select MOS transistor for making said memory cell section conducting to said first common signal line, and a second select MOS transistor with a threshold voltage different from that of said first select MOS transistor for making said memory cell section conducting to said second common signal line.

21. A nonvolatile semiconductor memory device according to claim 2, wherein each of said plurality of memory cell unit contains a first select MOS transistor for making said memory cell section conducting to said first common signal line, and a second select MOS transistor with a threshold voltage different from that of said first select MOS transistor for making said memory cell section conducting to said second common signal line.

25. A nonvolatile semiconductor memory device according to claim 1, wherein

each of said plurality of memory cell units each containing a first select MOS transistor and a second select MOS transistor contains at least a first memory cell unit and a second memory cell unit,

said first and second memory cell units constituting a subarray in such a manner that they share gate electrodes of said first and second select MOS transistors as a first and a second select gate, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

26. A nonvolatile semiconductor memory device according to claim 2, wherein

each of said plurality of memory cell units contains at least a first memory cell unit and a second memory cell unit, and said at least one select MOS transistor contains a first select MOS transistor and a second select MOS transistor,

said first and second memory cell units constituting a subarray in such a manner that they share gate electrodes of said first and second select MOS transistors as a first and a second select gate, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

29. A nonvolatile semiconductor memory device according to claim 25, further comprising means for applying a read select gate voltage to the first and second select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, both of said first and second select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read from, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and both of said first and second select MOS transistors in said second memory cell unit are made conducting.

30. A nonvolatile semiconductor memory device according to claim 26, further comprising means for applying a read select gate voltage to the first and second select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, both of said first and second select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read from, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and both of said first and second select MOS transistors in said second memory cell unit are made conducting.

33. A nonvolatile semiconductor memory device according to claim 25, further comprising means for applying a write select gate voltage to said first and second select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, said first select MOS transistor is made conducting, said second select MOS transistor is made nonconducting in said first memory cell unit and said first select MOS transistor is made nonconducting, said second select MOS transistor is made conducting or nonconducting in said second memory cell unit, and when the data is written into said second memory cell unit, said second select MOS transistor is made conducting, said first select MOS transistor is made nonconducting in said second memory cell unit and said second select MOS transistor is made nonconducting, said first select MOS transistor is made conducting or nonconducting in said second memory cell unit.

34. A nonvolatile semiconductor memory device according to claim 26, further comprising means for applying a write select gate voltage to said first and second select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, said first select MOS transistor is made conducting, said second select MOS transistor is made nonconducting in said first memory cell unit and said first select MOS transistor is made nonconducting, said second select MOS transistor is made conducting or nonconducting in said second memory cell unit, and when the data is written into said second memory cell unit, said second select MOS transistor is made conducting, said first select MOS transistor is made nonconducting in said second memory cell unit and said second select MOS transistor is made nonconducting, said first select MOS transistor is made conducting or nonconducting in said second memory cell unit.

37. A nonvolatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cell units contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor.

38. A nonvolatile semiconductor memory device according to claim 2, wherein each of said plurality of memory cell units contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor.

41. A nonvolatile semiconductor memory device according to claim 1, wherein

each of said plurality of memory cell units contains at least a first memory cell unit and a second memory cell unit,

each of said first and second memory cell units containing two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, and constituting a subarray in such a manner that they share gate electrodes of said first to third select MOS transistors as a first to third select gates, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

42. A nonvolatile semiconductor memory device according to claim 2, wherein

each of said plurality of memory cell units contains at least a first memory cell unit and a second memory cell unit,

each of said first and second memory cell units containing two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, and constituting a subarray in such a manner that they share gate electrodes of said first to third select MOS transistors as a first to third select gates, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

45. A nonvolatile semiconductor memory device according to claim 25, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

46. A nonvolatile semiconductor memory device according to claim 26, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

49. A nonvolatile semiconductor memory device according to claim 41, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

50. A nonvolatile semiconductor memory device according to claim 42, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

53. A nonvolatile semiconductor memory device according to claim 41, further comprising means for applying a read select gate voltage to the first to third select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, said first to third select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read out, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and said first to third select MOS transistors in said second memory cell unit are made conducting.

54. A nonvolatile semiconductor memory device according to claim 42, further comprising means for applying a read select gate voltage to the first to third select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, said first to third select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read out, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and said first to third select MOS transistors in said second memory cell unit are made conducting.

57. A nonvolatile semiconductor memory device according to claim 41, further comprising means for applying a write select gate voltage to said first to third select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, both of said first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said first memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor in said second memory cell unit is made nonconducting, and when the data is written into said second memory cell unit, both of first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said second memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

58. A nonvolatile semiconductor memory device according to claim 42, further comprising means for applying a write select gate voltage to said first to third select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, both of said first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said first memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor in said second memory cell unit is made nonconducting, and when the data is written into said second memory cell unit, both of first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said second memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

61. A nonvolatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cell units contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line ,and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected to said second common signal line and a fourth select MOS transistor connected to said memory cell section, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor, and said third select MOS transistor having a threshold voltage different from that of said fourth select MOS transistor.

62. A nonvolatile semiconductor memory device according to claim 2, wherein each of said plurality of memory cell units contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line ,and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected to said second common signal line and a fourth select MOS transistor connected to said memory cell section, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor, and said third select MOS transistor having a threshold voltage different from that of said fourth select MOS transistor.

65. A nonvolatile semiconductor memory device according to claim 1, wherein each of said plurality of memory cell units contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series, for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected in series to said second common signal line and a fourth select MOS transistors connected to said memory cell section, and wherein said first memory cell unit in which said first, second, third, and fourth select MOS transistors have a first, second, third, and fourth threshold voltages of Vth1, Vth2, Vth3, and Vth4 respectively and said second memory cell unit in which said first, second, third, and fourth select MOS transistors have a fifth, sixth, seventh, and eighth threshold voltages of Vth5, Vth6, vth7, and Vth8 constitute a subarray in such a manner that they share gate electrodes of said first to fourth select MOS transistors as a first to fourth select gates, respectively, and if Vth1 is larger than Vth5, Vth2 is smaller than Vth6, conversely, if Vth1 is smaller than Vth5, Vth2 is larger than Vth6, and that, if Vth3 is larger than Vth7, Vth4 is smaller than Vth8, conversely, if Vth3 is smaller than Vth7, Vth4 is larger than Vth8.

66. A nonvolatile semiconductor memory device according to claim 2, wherein each of said plurality of memory cell units contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series, for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected in series to said second common signal line and a fourth select MOS transistors connected to said memory cell section, and wherein said first memory cell unit in which said first, second, third, and fourth select MOS transistors have a first, second, third, and fourth threshold voltages of Vth1, Vth2, Vth3, and Vth4 respectively and said second memory cell unit in which said first, second, third, and fourth select MOS transistors have a fifth, sixth, seventh, and eighth threshold voltages of Vth5, Vth6, Vth7, and Vth8 constitute a subarray in such a manner that they share gate electrodes of said first to fourth select MOS transistors as a first to fourth select gates, respectively, and if Vth1 is larger than Vth5, Vth2 is smaller than Vth6, conversely, if Vth1 is smaller than Vth5, Vth2 is larger than Vth6, and that, if Vth3 is larger than Vth7, Vth4 is smaller than Vth8, conversely, if Vth3 is smaller than Vth7, Vth4 is larger than Vth8.

69. A nonvolatile semiconductor memory device according to claim 65, wherein said first threshold voltage Vth1 is equal to said sixth threshold voltage Vth6, said second threshold voltage Vth2 is equal to said fifth threshold voltage Vth5, said third threshold voltage Vth3 is equal to said eighth threshold voltage Vth8, and said fourth threshold voltage Vth4 is equal to said seventh threshold voltage Vth7.

70. A nonvolatile semiconductor memory device according to claim 66, wherein said first threshold voltage Vth1 is equal to said sixth threshold voltage Vth6, said second threshold voltage Vth2 is equal to said fifth threshold voltage Vth5, said third threshold voltage Vth3 is equal to said eighth threshold voltage Vth8, and said fourth threshold voltage Vth4 is equal to said seventh threshold voltage Vth7.

73. A nonvolatile semiconductor memory device according to claim 65, further comprising means for applying a read select gate voltage to the first to forth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is read from, said first to fourth select MOS transistors in said first memory cell unit are made conducting and at least one of said first to fourth select MOS transistors in said second memory cell unit is made nonconducting, and when the memory cell section in said second memory cell unit is read from, at least one of said first to fourth select MOS transistors in said first memory cell unit is made nonconducting and said first to fourth select MOS transistors in said second memory cell unit are made conducting.

74. A nonvolatile semiconductor memory device according to claim 66, further comprising means for applying a read select gate voltage to the first to forth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is read from, said first to fourth select MOS transistors in said first memory cell unit are made conducting and at least one of said first to fourth select MOS transistors in said second memory cell unit is made nonconducting, and when the memory cell section in said second memory cell unit is read from, at least one of said first to fourth select MOS transistors in said first memory cell unit is made nonconducting and said first to fourth select MOS transistors in said second memory cell unit are made conducting.

77. A nonvolatile semiconductor memory device according to claim 65, further comprising means for applying a write select gate voltage to said first to fourth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is programmed into, both of said first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistor is made nonconducting in said first memory cell unit, at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said memory cell unit, and when the memory cell section in said second memory cell unit is programmed into, both of first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistors is made nonconducting in each of said plurality of memory cell units and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

78. A nonvolatile semiconductor memory device according to claim 66, further comprising means for applying a write select gate voltage to said first to fourth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is programmed into, both of said first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistor is made nonconducting in said first memory cell unit, at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said memory cell unit, and when the memory cell section in said second memory cell unit is programmed into, both of first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistors is made nonconducting in each of said plurality of memory cell units and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

3. A nonvolatile semiconductor memory device comprising;

a first to third common signal lines;

at least one word line; and

a memory cell array in which contains first and second memory cell units, said first and second memory cell units sharing said at least one word line and each having a first end and a second end, each of said first and second memory cell units containing a memory cell section having at least one nonvolatile memory cell;

wherein

said first end of said first memory cell unit is connected to said first common signal line;

said second end of said first memory cell unit and said second end of said second memory cell unit share a contact and are connected to said second common signal line; and

said first end of said second memory cell unit is connected to said third common signal line.

8. A nonvolatile semiconductor memory device according to claim 3, further comprising means for biasing at least one of said first common signal line and said third common signal line to a read potential and keeping said second common signal line at a read unselected potential and for biasing said second common signal to a read potential and keeping at least one of said first and third common signal lines at a read unselected potential in reading the data in at least one of said plurality of memory cell units.

13. A nonvolatile semiconductor memory device according to claim 3, further comprising means for biasing at least one of said first common signal line and said third common signal line to a "1" program potential or a "0" program potential according to the programming data and keeping said second common signal line at a program unselected potential, and for biasing said second common signal line to a "1" pro ram potential or a "0" program potential according to the programming data and keeping at least one of said first and third common signal lines at a program unselected potential in programming the data in at least one of said plurality of memory cell units.

17. A nonvolatile semiconductor memory device according to claim 3, in which said plurality of memory cell units constitute a plurality of memory blocks each having a select gate and each of said plurality of memory cell units contains at least one select MOS transistor for making said memory cell section conducting to at least one of said first to third common signal lines, further comprising means for applying an unselected gate voltage to the select gate in an unselected block so that the select MOS transistors in the plurality of memory cell units in said unselected block not to be read from or written into may turn off, in reading and programming the data from and into at least one of said plurality of memory cell units.

22. A nonvolatile semiconductor memory device according to claim 3, wherein said first memory cell unit contains a first select MOS transistor for making said memory cell section conducting to said first common signal line, and a second select MOS transistor with a threshold voltage different from that of said first select MOS transistor for making said memory cell section conducting to said second common signal line, and said second memory cell unit contains a third select MOS transistor for making said memory cell section conducting to said third common signal line and a fourth select MOS transistor with a threshold voltage different from that of said third select MOS transistor for making said memory cell section conducting to said second common signal line.

27. A nonvolatile semiconductor memory device according to claim 3, wherein

each of said first and second memory cell units contains a first select MOS transistor and a second select MOS transistor,

said first and second memory cell units constituting a subarray in such a manner that they share gate electrodes of said first and second select MOS transistors as a first and a second select gate, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

31. A nonvolatile semiconductor memory device according to claim 27, further comprising means for applying a read select gate voltage to the first and second select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, both of said first and second select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read from, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and both of said first and second select MOS transistors in said second memory cell unit are made conducting.

35. A nonvolatile semiconductor memory device according to claim 27, further comprising means for applying a write select gate voltage to said first and second select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, said first select MOS transistor is made conducting, said second select MOS transistor is made nonconducting in said first memory cell unit and said first select MOS transistor is made nonconducting, said second select MOS transistor is made conducting or nonconducting in said second memory cell unit, and when the data is written into said second memory cell unit, said second select MOS transistor is made conducting, said first select MOS transistor is made nonconducting in said second memory cell unit and said second select MOS transistor is made nonconducting, said first select MOS transistor is made conducting or nonconducting in said second memory cell unit.

39. A nonvolatile semiconductor memory device according to claim 3, wherein said first memory cell unit contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor, and said second memory cell unit contains two select MOS transistors connected in series for making said memory cell section conducting to said third common signal line, that is, a fourth select MOS transistor connected to said third common signal line, and a fifth select MOS transistor connected to said memory cell section, and moreover a sixth select MOS transistor for making said memory cell section conducting to said second common signal line, said fourth select MOS transistor have a threshold voltage different from that of said fifth select MOS transistor.

43. A nonvolatile semiconductor memory device according to claim 3, wherein

said first memory cell unit containing two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, said second memory cell unit contains two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line, that is, a fourth select MOS transistor connected to said third common signal line, and a fifth select MOS transistor connected to said memory cell section, and moreover a sixth select MOS transistor for making said memory cell section conducting to said second common signal line, said fourth select MOS transistor have a threshold voltage different from that of said fifth select MOS transistor, and constituting a subarray in such a manner that they share gate electrodes of said first to third select MOS transistors as a first to third select gates, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said fifth select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said fourth select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said fifth select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said fourth select MOS transistor in said second memory cell unit.

47. A nonvolatile semiconductor memory device according to claim 27, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

51. A nonvolatile semiconductor memory device according to claim 43, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said fifth select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said fourth select MOS transistor in said second memory cell unit.

55. A nonvolatile semiconductor memory device according to claim 43, further comprising means for applying a read select gate voltage to the first to sixth select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, said first to third select MOS transistors in said first memory cell unit are made conducting and at least one of said fourth and fifth select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read out, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and said fourth and sixth select MOS transistors in said second memory cell unit are made conducting.

59. A nonvolatile semiconductor memory device according to claim 43, further comprising means for applying a write select gate voltage to said first to sixth select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, both of said first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said first memory cell unit and at least one of said fourth select MOS transistor and said fifth select MOS transistor in said second memory cell unit is made nonconducting, and when the data is written into said second memory cell unit, both of said fourth and fifth select MOS transistors are made conducting, said sixth select MOS transistor is made nonconducting in said second memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

63. A nonvolatile semiconductor memory device according to claim 3, wherein said first memory cell unit contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected to said second common signal line and a fourth select MOS transistor connected to said memory cell section, said second memory cell unit contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line, that is, a fifth select MOS transistor connected to said third common signal line, and a sixth select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line that is a seventh select MOS transistor connected to said second common signal line and an eighth select MOS transistor connected to said memory cell section, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor, said third select MOS transistor having a threshold voltage different from that of said fourth select MOS transistor, said fifth select MOS transistor having a threshold voltage different from that of said sixth select MOS transistor, and said seventh select MOS transistor having a threshold voltage different from that of said eighth select MOS transistor.

67. A nonvolatile semiconductor memory device according to claim 3, wherein each of said first and second memory cell unit contains two select MOS transistors connected in series for making said memory cell section conducting to said first or third common signal line, that is, a first select MOS transistors of said first and second memory cell units connected to said first and third common signal lines, respectively, and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series, for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected in series to said second common signal line and a fourth select MOS transistors connected to said memory cell section, and wherein said first memory cell unit in which said first, second, third, and fourth select MOS transistors have a first, second, third, and fourth threshold voltages of Vth1, Vth2, Vth3, and Vth4 respectively and said second memory cell unit in which said first, second, third, and fourth select MOS transistors have a fifth, sixth, seventh, and eighth threshold voltages of Vth5, Vth6, Vth7, and Vth8 constitute a subarray in such a manner that they share gate electrodes of said first to fourth select MOS transistors as a first to fourth select gates, respectively, and if Vth1 is larger than Vth5, Vth2 is smaller than Vth6, conversely, if Vth1 is smaller than Vth5, Vth2 is larger than Vth6, and that, if Vth3 is larger than Vth7, Vth4 is smaller than Vth8, conversely, if Vth3 is smaller than Vth7, Vth4 is larger than Vth8.

71. A nonvolatile semiconductor memory device according to claim 67, wherein said first threshold voltage Vth1 is equal to said sixth threshold voltage Vth6, said second threshold voltage vth2 is equal to said fifth threshold voltage Vth5, said third threshold voltage Vth3 is equal to said eighth threshold voltage Vth8, and said fourth threshold voltage Vth4 is equal to said seventh threshold voltage Vth7.

75. A nonvolatile semiconductor memory device according to claim 67, further comprising means for applying a read select gate voltage to the first to forth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is read from, said first to fourth select MOS transistors in said first memory cell unit are made conducting and at least one of said first to fourth select MOS transistors in said second memory cell unit is made nonconducting, and when the memory cell section in said second memory cell unit is read from, at least one of said first to fourth select MOS transistors in said first memory cell unit is made nonconducting and said first to fourth select MOS transistors in said second memory cell unit are made conducting.

79. A nonvolatile semiconductor memory device according to claim 67, further comprising means for applying a write select gate voltage to said first to fourth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is programmed into, both of said first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistor is made nonconducting in said first memory cell unit, at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said memory cell unit, and when the memory cell section in said second memory cell unit is programmed into, both of first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistors is made nonconducting in each of said plurality of memory cell units and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

4. A nonvolatile semiconductor memory device comprising:

a first and second common signal lines;

at least one word line; and

a memory cell array in which contains first and second memory cell units, each of said first and second memory cell units sharing said at least one word line and each having a first end and a second end, each of said first and second memory cell units containing a memory cell section having at least one nonvolatile memory cell;

wherein

said first end of said first memory cell unit and said first end of said second memory cell unit share a contact and are connected to said first common signal line; and

said second end of said first memory cell unit and said second end of said second memory cell unit share a contact and are connected to said second common signal line.

9. A nonvolatile semiconductor memory device according to claim 4, further comprising means for biasing said first common signal line, to which said first end of each of said plurality of memory cell units is connected, to a read potential and keeping said second common signal line, to which said second end of each of said plurality of memory cell units is connected, at a read unselected potential in reading the data in at least one of said plurality of memory cell units.

14. A nonvolatile semiconductor memory device according to claim 4, further comprising means for biasing said first common signal line, to which said first end of each of said plurality of memory cell units is connected, to a "1" program potential or a "0" program potential according to the programming data and keeping at least one of said third common signal line, to which said second end of each of said plurality of memory cell units is connected, at a program unselected potential in programming the data in at least one of said plurality of memory cell units.

18. A nonvolatile semiconductor memory device according to claim 4, in which said plurality of memory cell units constitute a plurality of memory blocks each having a select gate and each of said plurality of memory cell units contains at least one select MOS transistor for making said memory cell section conducting to at least one of said first and second common signal lines, further comprising means for applying an unselected gate voltage to the select gate in an unselected block so that the select MOS transistors in the plurality of memory cell units in said unselected block not to be read from or written into may turn off, in reading and programming the data from and into at least one of said plurality of memory cell units.

23. A nonvolatile semiconductor memory device according to claim 4, wherein said first memory cell unit contains a first select MOS transistor for making said memory cell section conducting to said first common signal line, and a second select MOS transistor with a threshold voltage different from that of said first select MOS transistor for making said memory cell section conducting to said second common signal line, and said second memory cell unit contains a third select MOS transistor for making said memory cell section conducting to said first common signal line, and a fourth select MOS transistor with a threshold voltage different from that of said third select MOS transistor for making said memory cell section conducting to said second common signal line.

28. A nonvolatile semiconductor memory device according to claim 4, wherein

each of said first and second memory cell units contains a first select MOS transistor and a second select MOS transistor,

said first and second memory cell units constituting a subarray in such a manner that they share gate electrodes of said first and second select MOS transistors as a first and a second select gate, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

32. A nonvolatile semiconductor memory device according to claim 28, further comprising means for applying a read select gate voltage to the first and second select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, both of said first and second select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read from, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and both of said first and second select MOS transistors in said second memory cell unit are made conducting.

36. A nonvolatile semiconductor memory device according to claim 28, further comprising means for applying a write select gate voltage to said first and second select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, said first select MOS transistor is made conducting, said second select MOS transistor is made nonconducting in said first memory cell unit and said first select MOS transistor is made nonconducting, said second select MOS transistor is made conducting or nonconducting in said second memory cell unit, and when the data is written into said second memory cell unit, said second select MOS transistor is made conducting, said first select MOS transistor is made nonconducting in said second memory cell unit and said second select MOS transistor is made nonconducting, said first select MOS transistor is made conducting or nonconducting in said second memory cell unit.

40. A nonvolatile semiconductor memory device according to claim 4, wherein each of said first and second memory cell units contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, said first select MOS transistor having a threshold voltage different from that or said second select MOS transistor.

44. A nonvolatile semiconductor memory device according to claim 4, wherein

each of said first and second memory cell units containing two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover a third select MOS transistor for making said memory cell section conducting to said second common signal line, and constituting a subarray in such a manner that they share gate electrodes of said first to third select MOS transistors as a first to third select gates, respectively, with

the threshold voltage of said second select MOS transistor in said first memory cell unit being lower than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is higher than the threshold voltage of said first select MOS transistor in said second memory cell unit, and

the threshold voltage of said second select MOS transistor in said first memory cell unit being higher than the threshold voltage of said second select MOS transistor in said second memory cell unit when the threshold voltage of said first select MOS transistor in said first memory cell unit is lower than the threshold voltage of said first select MOS transistor in said second memory cell unit.

48. A nonvolatile semiconductor memory device according to claim 28, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

52. A nonvolatile semiconductor memory device according to claim 44, wherein the threshold voltage of said first select MOS transistor in said first memory cell unit is equal to the threshold voltage of said second select MOS transistor in said second memory cell unit, and the threshold voltage of said second select MOS transistor in said first memory cell unit is equal to the threshold voltage of said first select MOS transistor in said second memory cell unit.

56. A nonvolatile semiconductor memory device according to claim 44, further comprising means for applying a read select gate voltage to the first to third select MOS transistors in said subarray selected in such a manner that when the data in said first memory cell unit is read out, said first to third select MOS transistors in said first memory cell unit are made conducting and at least one of said first and second select MOS transistors in said second memory cell unit is made nonconducting, and when the data in said second memory cell unit is read out, at least one of said first and second select MOS transistors in said first memory cell unit is made nonconducting and said first to third select MOS transistors in said second memory cell unit are made conducting.

60. A nonvolatile semiconductor memory device according to claim 44, further comprising means for applying a write select gate voltage to said first to third select MOS transistors in said subarray selected in such a manner that when the data is written into said first memory cell unit, both of said first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said first memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor in said second memory cell unit is made nonconducting, and when the data is written into said second memory cell unit, both of first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said second memory cell unit and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

64. A nonvolatile semiconductor memory device according to claim 4, wherein each of said plurality of memory cell units contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line ,and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected to said second common signal line and a fourth select MOS transistor connected to said memory cell section, said first select MOS transistor having a threshold voltage different from that of said second select MOS transistor, and said third select MOS transistor having a threshold voltage different from that of said fourth select MOS transistor.

68. A nonvolatile semiconductor memory device according to claim 4, wherein each of said plurality of memory cell units contains two select MOS transistors connected in series for making said memory cell section conducting to said first common signal line, that is, a first select MOS transistor connected to said first common signal line, and a second select MOS transistor connected to said memory cell section, and moreover two select MOS transistors connected in series, for making said memory cell section conducting to said second common signal line, that is, a third select MOS transistor connected in series to said second common signal line and a fourth select MOS transistors connected to said memory cell section, and wherein said first memory cell unit in which said first, second, third, and fourth select MOS transistors have a first, second, third, and fourth threshold voltages of Vth1, Vth2, Vth3, and Vth4 respectively and said second memory cell unit in which said first, second, third, and fourth select MOS transistors have a fifth, sixth, seventh, and eighth threshold voltages of Vth5, Vth6, Vth7, and Vth8 constitute a subarray in such a manner that they share gate electrodes of said first to fourth select MOS transistors as a first to fourth select gates, respectively, and if Vth1 is larger than Vth5, Vth2 is smaller than Vth6, conversely, if Vth1 is smaller than Vth5, Vth2 is larger than Vth6, and that, if Vth3 is larger than Vth7, Vth4 is smaller than Vth8, conversely, if Vth3 is smaller than Vth7, Vth4 is larger than Vth8.

72. A nonvolatile semiconductor memory device according to claim 68, wherein said first threshold voltage Vth1 is equal to said sixth threshold voltage Vth6, said second threshold voltage Vth2 is equal to said fifth threshold voltage Vth5, said third threshold voltage Vth3 is equal to said eighth threshold voltage Vth8, and said fourth threshold voltage Vth4 is equal to said seventh threshold voltage Vth7.

76. A nonvolatile semiconductor memory device according to claim 68, further comprising means for applying a read select gate voltage to the first to forth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is read from, said first to fourth select MOS transistors in said first memory cell unit are made conducting and at least one of said first to fourth select MOS transistors in said second memory cell unit is made nonconducting, and when the memory cell section in said second memory cell unit is read from, at least one of said first to fourth select MOS transistors in said first memory cell unit is made nonconducting and said first to fourth select MOS transistors in said second memory cell unit are made conducting.

80. A nonvolatile semiconductor memory device according to claim 68, further comprising means for applying a write select gate voltage to said first to fourth select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is programmed into, both of said first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistor is made nonconducting in said first memory cell unit, at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said memory cell unit, and when the memory cell section in said second memory cell unit is programmed into, both of first and second select MOS transistors are made conducting, at least one of said third and fourth select MOS transistors is made nonconducting in each of said plurality of memory cell units and at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first memory cell unit.

5. A nonvolatile semiconductor memory device comprising:

a first to third common signal lines;

at least one word line; and

a memory cell array in which contains first to third memory cell units arranged in a matrix, said first to third memory cell units sharing said at least one word line, said first to third memory cell units each of which contains a memory cell section having at least one nonvolatile memory cell and has a first end and a second end;

wherein

said first end of said first memory cell unit is connected to said first common signal line;

said second end of first memory cell unit and said second end of said second memory cell unit and said second end of said third memory cell unit share a contact and are connected to said second common signal line; and

said first end of said second memory cell unit and said first end of said third memory cell unit share a contact are connected to said third common signal line.

10. A nonvolatile semiconductor memory device according to claim 5, further comprising means for biasing at least one of said first common signal line and said third common signal line to a read potential and keeping said second common signal line at a read unselected potential, and for biasing said second common signal to a read potential and keeping at least one of said first and third common signal lines at a read unselected potential in reading the data in at least one of said plurality of memory cell units.

15. A nonvolatile semiconductor memory device according to claim 5, further comprising means for biasing at least one of said first common signal line and said third common signal line to a "1" program potential or a "0" program potential according to the programming data and keeping said second common signal line at a program unselected potential, and for biasing said second common signal line to a "1" program potential or a "0" program potential according to the programming data and keeping said first and second common signal lines at a program unselected potential in programming the data in at least one of said plurality of memory cell units.

19. A nonvolatile semiconductor memory device according to claim 5, in which said plurality of memory cell units constitute a plurality of memory blocks each having a select gate and each of said plurality of memory cell units contains at least one select MOS transistor for making said memory cell section conducting to at least one of said first to third common signal lines, further comprising means for applying an unselected gate voltage to the select gate in an unselected block so that the select MOS transistors in the plurality of memory cell units in said unselected block not to be read from or written into may turn off, in reading and programming the data from and into at least one of said plurality of memory cell units.

24. A nonvolatile semiconductor memory device according to claim 5, wherein said first memory cell unit contains a first select MOS transistor for making said memory cell section conducting to said first common signal line, and a second select MOS transistor with a threshold voltage different from that of said first select MOS transistor for making said memory cell section conducting to said second common signal line, said second memory cell unit contains a third select MOS transistor for making said memory cell section conducting to said third common signal line, and a fourth select MOS transistor with a threshold voltage different from that of said third select MOS transistor for making said memory cell section conducting to said second common signal line, and said third memory cell unit contains a fifth select MOS transistor for making said memory cell section conducting to said third common signal line, and a sixth select MOS transistor with a threshold voltage different from that of said fifth select MOS transistor for making said memory cell section conducting to said second common signal line.

81. A nonvolatile semiconductor memory device according to claim 5, wherein said memory cell unit contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section to said first common signal line (a first select MOS transistor connected to said first common signal line and a second select MOS transistor connected to said memory cell section), and a third select MOS transistor for making said memory cell section conducting to said second common signal line, at least one of the threshold voltages of said first to third select MOS transistors different from the rest.

82. A nonvolatile semiconductor memory device according to claim 5, wherein said memory cell unit contains a memory cell section having at least a single nonvolatile memory cell, two select MOS transistors connected in series for making said memory cell section to said first common signal line (a first select MOS transistor connected to said first common signal line and a second select MOS transistor connected to said memory cell section), and a third select MOS transistor for making said memory cell section conducting to said second common signal line, and wherein said first memory cell unit in which said first select MOS transistor has a first threshold voltage of Vth1, said second select MOS transistor has a second threshold voltage of Vth2, said third select MOS transistor has a third threshold voltage of Vth3, said second memory cell unit in which said first select MOS transistor has a fourth threshold voltage of Vth4, said second select MOS transistor has a fifth threshold voltage of Vth5, said third select MOS transistor has a sixth threshold voltage of Vth6, and said third memory cell unit in which said first select MOS transistor has a seventh threshold voltage of Vth7, said second select MOS transistor has an eighth threshold voltage of Vth8, said third select MOS transistor has a ninth threshold voltage of Vth9 constitute a subarray in such a manner that they share the gate electrode of said first select MOS transistor, that of said second select MOS transistor, and that of said third select MOS transistor as a first, second, and third select gates, with at least one of said first threshold voltage Vth1, said fourth threshold voltage Vth4, and said seventh threshold voltage Vth7 different from the rest, at least one of said second threshold voltage Vth2, said fifth threshold voltage Vth5, and said eighth threshold voltage Vth8 different from the rest, and at least one of said third threshold voltage Vth3, said sixth threshold voltage vth6, and said ninth threshold voltage Vth9 different from the rest.

83. A nonvolatile semiconductor memory device according to claim 82, wherein said first threshold voltage Vth1, said fifth threshold voltage Vth5, and said ninth threshold voltage Vth9 are equal to each other, said second threshold voltage Vth2, said third threshold voltage Vth3, said fourth threshold voltage Vth4, said sixth threshold voltage Vth6, said seventh threshold voltage Vth7, and said eighth threshold voltage Vth8 are equal to each other.

84. A nonvolatile semiconductor memory device according to claim 82, wherein said first memory cell unit, said second memory cell unit, and said third memory cell unit are arranged alternately to form said subarray.

85. A nonvolatile semiconductor memory device according to claim 82, further comprising means for applying a read select gate voltage to the first, second, and third select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is read from, said first, second, and third select MOS transistors in said first memory cell unit are made conducting, at least one of said first, second, and third select MOS transistors in said second memory cell unit is made nonconducting, and at least one of said first, second, and third select MOS transistors in said third memory cell unit is made nonconducting, and when the memory cell section in said second memory cell unit is read from, said first, second, and third select MOS transistors in said second memory cell unit are made conducting, at least one of said first, second, and third select MOS transistors in said first memory cell unit is made nonconducting and at least one of said first, second, and third select MOS transistors in said third memory cell unit is made nonconducting, and when the memory cell section in said third memory cell unit is read from, said first, second, and third select MOS transistors in said third memory cell unit are made conducting, at least one of said first, second, and third select MOS transistors in said first memory cell unit is made nonconducting and at least one of said first, second, and third select MOS transistors in said second memory cell unit is made nonconducting.

86. A nonvolatile semiconductor memory device according to claim 82, further comprising means for applying a write select gate voltage to said first, second, and third select MOS transistors in said subarray selected in such a manner that when the memory cell section in said first memory cell unit is programmed into, both of said first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said first memory cell unit, at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said second and third memory cell units, and when the memory cell section in said second memory cell unit is programmed into, both of said first and second select MOS transistors are made conducting, said third select MOS transistor is made nonconducting in said second memory cell, at least one of said first select MOS transistor and said second select MOS transistor is made nonconducting in said first and third memory cell units, and when the memory cell section in said third memory cell unit is programmed into, said third select MOS transistor is made conducting, at least one of said first and second select MOS transistors is made nonconducting in said third memory cell unit, and said third select MOS transistors are made nonconducting in said first and second memory cell units.