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Method and apparatus for controlling memory address hold time

  • US 5,940,337 A
  • Filed: 10/23/1997
  • Issued: 08/17/1999
  • Est. Priority Date: 10/23/1997
  • Status: Expired due to Term
First Claim
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1. A method of accessing memory, comprising the steps of:

  • generating a latch clock signal and an equalization signal when any of a predefined set of address signals change value;

    responding to the latch clock signal by storing a predecoded address signal in a latch;

    responding to the equalization signal by equalizing I/O lines;

    decoding a combination of a first subset of the predefined set of address signals and the predecoded address signal stored in the latch to generate a decoded address signal; and

    activating memory lines in accordance with the decoded address signal.

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