Self-organizing circuits

• US 5,940,529 A
• Filed: 11/26/1996
• Issued: 08/17/1999
• Est. Priority Date: 07/25/1994
• Status: Expired due to Term

• Current Assignee: Buckley B. Shawn
• Original Assignee: Buckley B. Shawn
• Inventors: Buckley, B. Shawn
• Primary Examiner(s): Couso, Jose L.
• Application Number:
  US08/756,971
• Time in Patent Office: 994 Days
• Field of Search: 382/155, 382/156, 382/157, 382/158, 382/159, 382/160, 382/190, 382/226, 382/227, 382/228, 382/229, 364/148, 395/2.11, 395/2.25, 395/2.26, 395/2.27, 395/2.4, 395/2.41, 395/2.46, 395/2.47, 395/2.48, 395/2.49, 395/2.52, 395/2.53, 395/2.54, 395/2.68, 395/2.72, 395/1 , 395/11, 395/20, 395/27, 395/50
• US Class Current: 382/155
• CPC Class Codes: G06N 3/004 Artificial life, i.e. computing arrangements simulating life

Abstract

A self-organizing system providing improved performance is composed of node subcircuits in two or three dimensional arrays of nodes which behave like neurons in the brain. Improvements in the learning rules use the time-filtered output of nodes to define memory traces. Spatial summation and spatial difference functions then determine how node branches will compete to produce various memory trace topologies such as roots and junctions. Roots begin as input patterns at the lowest level of the circuit and grow towards output nodes at the highest level; roots are attracted to output nodes and to other roots as they grow. Roots connect or branch at junctions which are identified by spatial functions. By modifying node properties and branch competition of nodes at root junctions, roots interact to create Boolean logic roles. Unsupervised (classical) learning results when roots associate with each other. Supervised (operant) learning regulates root junction logic to assure that sequential or combinational system input patterns produce the proper system outputs. Punish or reward signals broadcast to all nodes are only acted on by memory trace root junction nodes. Implementation is in digital and analog circuitry as well as hardware and software embodiments.

Claims

1. A self-organizing system having a system input signal with constituent elements comprising:

self-organizing means for providing a system output signal corresponding to the analysis of the constituent elements of said system input signal, said self-organizing means further comprising a plurality of identical subcircuits, each subcircuit having a changeable state and organized into a plurality of levels;

an input set composed of both the constituent elements of said system input signal and the output state of each said subcircuit, each subcircuit adapted to receive input messages from at least one element of the input set and which input messages can originate from other subcircuits in previous levels, in the same level and in higher levels;

voting means for voting on the state of each said subcircuit based on a comparison of the relative amounts of positive and negative weighting which the input messages have on each subcircuit;

weight modification means of each subcircuit for modifying the weighting of the input messages based in part upon space functions of subcircuits.

2. The system of claim 1 wherein said weighting means further comprises universal means for additionally modifying the weighting of the input messages of said subcircuits using universal punish and reward signals directed to all subcircuits.

3. The system of claim 2 wherein said weighting means further comprises comparison means for comparing the relative amount of positive and negative input to said voting means, wherein the comparison in conjunction with said universal means determines whether weight modification of the subcircuit will change from its present value.

4. The system of claim 3 wherein the amount of weight modification is limited by the comparison of the relative amounts of positive and negative input provided by said comparison means.

5. The system of claim 1 wherein said weighting of at least a portion of input messages in the analysis of a first pattern of constituent elements of said system input signal is held fixed during the analysis of a second pattern of constituent elements.

6. The system of claim 1 wherein said space functions can include spatial summation functions and spatial difference functions.

7. The system of claim 6 wherein said spatial summation functions for a subcircuit include iterative calculations summing the values of said spatial summation function in its local neighborhood of subcircuits, which neighborhood can include the subcircuit itself.

8. The system of claim 7 wherein said spatial summation functions for a subcircuit include the sum of subcircuits in its local neighborhood which have the proper time-filtered state.

9. The system of claim 7 wherein said spatial summation functions for a subcircuit include the sum of the spatial summation values in its local neighborhood combined with a source value.

10. The system of claim 9 wherein said spatial summation functions for a subcircuit includes a source value based upon the time-filtered state of the subcircuit.

11. The system of claim 9 wherein said spatial summation functions for a subcircuit includes a source value based upon the sum of the subcircuits in its local neighborhood which have the proper time-filtered state.

12. The system of claim 9 wherein said spatial summation functions for a subcircuit includes a source value based in part on universal punish and reward signals directed to all subcircuits.

13. The system of claim 6 wherein said spatial difference functions for a subcircuit include the sum of the differences in an argument function between the subcircuit and other subcircuits in its local neighborhood.

14. The system of claim 6 wherein said spatial difference functions for a subcircuit include the ranking of an argument function among the subcircuits of its local neighborhood.

15. The system of claim 14 wherein said argument function for a subcircuit includes the sum of the argument function values of subcircuits in its local neighborhood combined with a source value based upon the time-filtered state of the subcircuit.

16. The system of claim 1 wherein the input messages from said same level to a subcircuit can include an input message of the subcircuit state.

17. The system of claim 16 wherein said input message of the subcircuit state is delayed in time from the subcircuit state.

18. The system of claim 1 wherein subcircuits which meet the proper time-filtered change of state criteria determine topological memory trace structures using said space functions.

19. The system of claim 18 wherein said memory trace structures include root structures having an elongated shape in which the number of subcircuits across the structure is smaller than the number of subcircuits along the structure.

20. The system of claim 19 wherein said root structures grow by incorporating target subcircuits into the root structure by modifying the weight of target subcircuit input messages originating from subcircuits already in the root structure.

21. The system of claim 20 wherein the direction of growth of said root structure is based in part upon the values of space functions of the subcircuits.

22. The system of claim 20 in which the growth of said root structures further elongates the root structure.

23. The system of claim 20 in which the growth of said root structures fills in concavities in the root structure.

24. The system of claim 20 in which the growth of said root structures branches the root structure into two or more elongated root structures.

25. The system of claim 18 in which the weighting of input messages of memory trace subcircuits is modified to produce different Boolean logic behavior of the subcircuit state.

26. The system of claim 25 in which the weighting of input messages of memory trace subcircuits is modified to produce OR/NOR-like behavior.

27. The system of claim 26 in which the memory trace subcircuits having their weighting modified are interior subcircuits identified by the values of space functions of the subcircuits.

28. The system of claim 18 in which the weighting of input messages of memory trace subcircuits is modified to produce different Boolean logic behavior of the subcircuit state based in part on universal punish and reward signals directed to all subcircuits.

29. The system of claim 28 in which the weighting of input messages of memory trace subcircuits is modified to produce OR/NOR-like behavior under universal reward signals and to produce AND/NAND-like behavior under universal punish signals.

30. The system of claim 29 in which the memory trace subcircuits having weighting modified are interior subcircuits identified by the values of space functions of the subcircuits.

31. The system of claim 28 in which the weighting of input messages of memory trace subcircuits is modified to hinder the progress of information through the memory trace structure under universal punish signals.

32. The system of claim 31 in which the memory trace subcircuits having weighting modified are interior subcircuits identified by the values of space functions of the subcircuits.

33. The system of claim 28 in which the weighting of input messages of memory trace subcircuits is modified to facilitate the progress of information through the memory trace structure under universal punish signals.

34. The system of claim 33 in which the memory trace subcircuits having weighting modified are interior subcircuits identified by the values of space functions of the subcircuits.

35. The system of claim 18 in which a computational threshold of a memory trace subcircuit is modified based in part on universal punish and reward signals directed to all subcircuits.

36. The system of claim 35 in which said computational threshold determines the topology characteristics of the memory trace identified by the values of space functions of the subcircuits.

37. The system of claim 1 in which said self-organizing system is implemented in software.

38. The system of claim 18 in which the progress of information through one memory trace structure is modified based upon the space functions of adjacent memory trace structures.

39. The system of claim 38 in which the progress of information through one memory trace structure is modified based upon the time difference between progress of information through adjacent memory trace structures.

40. The system of claim 1 in which said system output signal is fed back to each said constituent element of the system input signal and further having said system output signal weighted to encourage the repeated circulation of information through said plurality of identical subcircuits.

41. The system of claim 1 in which a portion of said identical subcircuits are coupled to other nearby subcircuits that encourage the repeated circulation of information through said plurality of identical subcircuits.

42. The system of claim 1 in which each said system output signal is identified during its weight modification as having either desirable or undesirable characteristics, said characteristics being later summed to provide a composite measure of the desirability of unknown constituent elements of said system input signal.

43. The system of claim 1 in which each said subcircuit is identified during its weight modification as having either desirable or undesirable characteristics, said characteristics being later summed to provide a composite measure of the desirability of unknown constituent elements of said system input signal.