Synchronous clock generator including a false lock detector

• US 5,940,609 A
• Filed: 08/29/1997
• Issued: 08/17/1999
• Est. Priority Date: 08/29/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Harrison, Ronnie M.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/921,236
• Time in Patent Office: 718 Days
• Field of Search: 395/559, 395/555, 395/558, 331/1 A, 331/DIG. 2, 375/376
• US Class Current: 713/503
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03L 2207/14 Preventing false-lock or pseudo-lock of the PLL
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal is comprised of a logic circuit for receiving first and second signals produced by the locked loop. The logic circuit determines if a predetermined phase relationship exists between the first and second signals and produces an output signal indicative of that determination.

Claims

1. A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal, comprising:

a delay line included in said locked loop, said delay line producing a signal at a 90°

tap thereof; and

a logic circuit including a flip-flop connected to receive the signal from the 90°

tap and the clock signal, said logic circuit for determining if a predetermined phase relationship exists between the signal from the 90°

tap and the clock signal and for producing an output signal indicative of said determination.

2. A false lock detector for use with a delay-locked loop which produces a plurality of output signals in response to a clock signal, comprising:

a delay line included in said delay-locked loop, said delay line producing a signal at a 90°

tap thereof; and

a logic circuit connected to receive first and second signals produced by the delay-locked loop, said logic circuit including a flip-flop connected to receive the signal from the 90°

tap and the clock signal, said signal from the 90°

tap having known states when said clock signal changes states, said logic circuit producing an output signal indicative of whether said signal from the 90°

tap is in said known states when said clock signal changes states.

3. A delay-locked loop having a false lock detector, comprising:

a delay line for receiving a clock signal and for producing a plurality of output signals each having a predetermined delay with respect to the clock signal;

a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; and

a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

4. The delay-locked loop of claim 3 wherein said feedback path comprises a phase detector responsive to certain of said plurality of output signals and a charge pump responsive to said phase detector, and wherein said output signal is input to said phase detector.

5. A synchronous clock generator having a false lock detector, comprising:

a receiver for receiving an external clock signal;

a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal;

a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line;

a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and

a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

6. The synchronous clock generator of claim 5 wherein said feedback path comprises a phase detector responsive to certain of said plurality of output signals and a charge pump responsive to said phase detector, and wherein said output signal is input to said phase detector.

7. A system, comprising:

a processor;

a memory controller;

a plurality of memory devices,

a first bus interconnecting said processor and said memory controller; and

a second bus interconnecting said memory controller and said memory devices;

each of said memory devices having a synchronous clock generator, comprising;

a receiver for receiving an external clock signal;

a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal;

a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line;

a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and

a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

8. An internal clock generator circuit, comprising:

a clock generator including a locked loop constructed to provide first and second internal clock signals, the first clock signal having a phase determined by first and second phase control signals applied to respective first and second control inputs of the clock generator;

a phase detector coupled to the clock generator to receive the first internal clock signal, the phase detector further receiving a reference clock signal, the phase detector being constructed to generate an output signal indicative of the phase of the first internal clock signal relative to the phase of the reference clock signal, the output signal being coupled to the first control input of the clock generator; and

a false lock detector coupled to the clock generator to receive the second internal clock signal and another clock signal coupled to or from the clock generator, the false lock detector generating a false lock signal responsive to a predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal, the false lock signal being applied to the second control input of the clock generator to alter the phase of the first internal clock signal.

9. The internal clock generator circuit of claim 8 wherein the other clock signal comprises a clock signal generated by the locked loop.

10. The internal clock generator circuit of claim 8 wherein the predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal comprises 90 degrees.

11. A delay locked loop, comprising:

a delay line receiving a reference clock signal and generating first and second delayed clock signals, the first delayed clock signal having a phase relative to the phase of the reference clock signal that is determined by a signal applied to a control terminal of the delay line;

a phase detector coupled to the delay line to receive the first delayed clock signal and coupled to receive the reference clock signal, the phase detector generating a signal at an output terminal indicative of the phase of the first delayed clock signal relative to the phase of the reference clock signal, the output terminal of the phase detector being coupled to the control terminal of the delay line; and

a false lock detector coupled to the delay line to receive the second delayed clock signal, the false lock detector being constructed to apply a signal to the control terminal of the delay line responsive to a predetermined characteristic of the second delayed clock signal indicative of a false lock condition of the delay locked loop.

12. The delay locked loop of claim 11 wherein the predetermined characteristic comprises the logic level of the second delayed clock signal at a transition of the first delayed clock signal.

13. The delay locked loop of claim 11 wherein the predetermined characteristic comprises the phase of the second delayed clock signal relative to the phase of the first delayed delayed clock signal.

14. A method of generating an internal clock signal, comprising:

adjusting the phase of the internal clock signal relative to a reference clock signal using a locked loop, the locked loop adjusting the phase of the internal clock signal as a function of the phase relationship between the internal clock signal and the reference clock signal in an attempt to maintain a predetermined phase relationship between the internal clock signal and the reference clock signal;

detecting a false lock condition of the locked-loop using at least one clock signal generated by the locked loop and another clock signal coupled to or from the locked loop; and

altering the phase of the internal clock signal in a single direction responsive to detecting the false lock condition.

15. The method of claim 14 wherein the false lock condition is detected using clock signals from the locked loop having respective phases that differ from each other by approximately 90 degrees.

16. The method of claim 14 wherein the false lock condition is detected by examining the logic level of the at least one clock signal generated by the locked loop at a transition of the other clock signal coupled to or from the locked loop.