Cache intervention from only one of many cache lines sharing an unmodified value
First Claim
1. A method of improving memory latency associated with a read-type operation issued by a requesting processing unit in a multiprocessor computer system, the computer system including a plurality of processing units each having an associated cache, comprising the steps of:
- loading a value from an address of a memory device into at least first and second caches;
marking the first and second caches as containing shared, unmodified copies of the value;
issuing a message from a requesting processing unit indicating that the requesting processing unit desires to read the value from the address of the memory device; and
transmitting a response from a given one of the first and second caches indicating that the given cache contains a shared, unmodified copy of the value and is the only cache entitled to directly source the value.
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Accused Products
Abstract
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.
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Citations
18 Claims
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1. A method of improving memory latency associated with a read-type operation issued by a requesting processing unit in a multiprocessor computer system, the computer system including a plurality of processing units each having an associated cache, comprising the steps of:
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loading a value from an address of a memory device into at least first and second caches; marking the first and second caches as containing shared, unmodified copies of the value; issuing a message from a requesting processing unit indicating that the requesting processing unit desires to read the value from the address of the memory device; and transmitting a response from a given one of the first and second caches indicating that the given cache contains a shared, unmodified copy of the value and is the only cache entitled to directly source the value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer system comprising:
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a memory device; an interconnect connected to said memory device; a plurality of processing units connected to said interconnect, each processing unit having a cache for storing values from said memory device, a given one of said caches further having means for indicating when said given cache contains a shared, unmodified copy of a value loaded from said memory device which value has also been contained as a shared, unmodified copy in at least one other of said caches; and means for transmitting a response from said given cache indicating that said given cache contains a shared, unmodified copy of the value and is the only cache entitled to directly source the value to a processing unit requesting to read the value. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification