Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains

• US 5,940,860 A
• Filed: 07/01/1996
• Issued: 08/17/1999
• Est. Priority Date: 07/01/1996
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hagersten, Erik E., Wood, David A., Hill, Mark Donald
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/677,012
• Time in Patent Office: 1,142 Days
• Field of Search: 711/141, 711/119, 711/120, 711/121, 711/124, 711/145, 711/147, 711/144, 395/200.43, 395/200.44, 395/200.46, 395/200.47, 395/200.78
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/622 State-only directory, i.e. not recording identity of sharing or owning nodes

Abstract

An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus. There is further included a protocol transformer logic coupled to the receiver logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device irrespective of the external device speed or protoco.

Claims

1. In a computer system having a computer node which has a common bus, a method for enabling an external device to share memory blocks having local physical addresses in a memory module at said computer node irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, each of said memory blocks having an associated Mtag for tracking a state associated with said each of said memory blocks, including a state for indicating that said each of said memory blocks is exclusive to said computer node, a state for indicating that said each of said memory blocks is shared by said computer node with said external device, and a state for indicating that said each of said memory blocks is invalid in said computer node, said method comprising:

receiving, at a coherence transformer coupled to said common bus, a first memory access request for a first memory block from said external device;

obtaining said first memory block, using said coherence transformer, from said common bus;

modifying, using said coherence transformer, a first Mtag associated with said first memory block in said memory module at said computer node to reflect that said external device is caching a valid copy of said first memory block; and

sending said valid copy of said first memory block from said coherence transformer to said external device.

2. The method of claim 1 wherein said first memory access request from said external device represents a request for an exclusive copy of said first memory block and said step of modifying said first Mtag includes a step of changing said first Mtag in said memory module to an invalid state.

3. The method of claim 2 further comprising a step of invalidating all valid copies of said first memory block at said computer node.

4. The method of claim 1 wherein said first memory access request from said external device represents either a request for an exclusive copy of said first memory block or a request for a shared copy of said first memory block, and said method further includes the steps of:

prior to said modifying step, examining said first Mtag associated with said first memory block; and

proceeding with said modifying step and said sending step only if said first Mtag does not represent an invalid state.

5. The method of claim 1 wherein said first memory access request from said external device represents a request for a shared copy of said first memory block and said step of modifying said first Mtag includes a step of changing said first Mtag in said memory module to a shared state.

6. The method of claim 5 further including the steps of:

prior to said modifying step, examining said first Mtag associated with said first memory block;

proceeding with said modifying step and said sending step only if said first Mtag does not represent an invalid state; and

if said first Mtag represents an invalid state, flagging an error condition.

7. The method of claim 1 further comprising the steps of:

receiving a write back request for said first memory block from said external device at said coherence transformer;

obtaining said valid copy of said first memory block, using said coherence transformer, from said external device;

writing said valid copy of said first memory block from said coherence transformer to said memory module at said computer node; and

modifying, using said coherence transformer, said first Mtag associated with said first memory block in said memory module at said computer node to reflect that said computer node has an exclusive copy of said first memory block.

8. The method of claim 7 wherein said writing of said valid copy of said first memory block step and said modifying of said first Mtag to reflect an exclusive copy step are accomplished via a single command issued by said coherence transformer.

9. The method of claim 1 wherein said memory blocks are shared between said external device and said computer node through said coherence transformer without requiring said coherence transformer to track whether a given memory block is cached by said external device.

10. In a computer system having a computer node which has a common bus, a method for enabling an external device to share memory blocks having local physical addresses in a memory module at said computer node through a coherence transformer coupled to a common bus of said computer node irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, each of said memory blocks having an associated Mtag for tracking a state associated with said each of said memory blocks, including a state for indicating that said each of said memory blocks is exclusive to said computer node, a state for indicating that said each of said memory blocks is shared by said computer node with said external device, and a state for indicating that said each of said memory blocks is invalid in said computer node, said method comprising:

receiving, at said memory module via said common bus, a first memory access request for a valid copy of a first memory block of said memory blocks from a progenitor of said first memory access request, said progenitor being an entity different from said coherence transformer;

responding to said first memory access request by sending a first copy of said first memory block, along with a first Mtag corresponding to said first memory block, from said memory module to said progenitor of said first memory access request;

examining, using said progenitor of said first memory access request, said first Mtag state; and

if said first Mtag state is invalid, issuing a second memory access request pertaining to said first memory block from said progenitor of said first memory access request to request said coherence transformer to service said second memory access request, thereby enabling said progenitor of said first memory access request to obtain said valid copy of said first memory block.

11. The method of claim 10 wherein said first memory access request represents a request for an exclusive copy of said first memory block, and said method, if said first Mtag state is invalid, further comprises:

obtaining a second copy of said first memory block, using said coherence transformer, from said external device;

invalidating said second copy of said first memory block at said external device;

sending, using said coherence transformer via said common bus, said second copy of said first memory block to said progenitor of said second memory access request; and

changing, using said coherence transformer via said common bus, said first Mtag state in said memory module to an exclusive state.

12. The method of claim 10 wherein said first memory access request represents a request for an exclusive copy of said first memory block, and said method, if said first Mtag state is shared, further comprises:

issuing said second memory access request pertaining to said first memory block from said progenitor of said first memory access request to request said coherence transformer to service said first memory access request.

13. The method of claim 12 further comprising:

invalidating a second copy of said first memory block at said external device;

obtaining said first copy of said first memory block, using said coherence transformer via said common bus, from said computer node;

invalidating all copies of said first memory block in said computer node;

sending said first copy of said first memory block from said coherence transformer to said progenitor of said second memory access request; and

changing, using said coherence transformer via said common bus, said first Mtag state to an exclusive state.

14. The method of claim 10 wherein said first memory access request represents a request for a shared copy of said first memory block, said method, if said first Mtag state is invalid, further comprises:

obtaining a second copy of said first memory block, using said coherence transformer, from said external device;

sending, using said coherence transformer via said common bus, said second copy of said first memory block to said progenitor of said second memory access request; and

changing, using said coherence transformer via said common bus, said first Mtag state in said memory module to a shared state.

15. The method of claim 14 further comprising:

if said first Mtag state is either a shared state or an exclusive state, flagging an error condition.

16. The method of claim 10 further comprising:

temporarily tracking said first memory block, including knowledge regarding a state of said first memory block in either said computer node or in said external device, in a temporary buffer associated with said coherence transformer; and

if a third memory access request pertaining to said first memory block appears on said common bus prior to said second memory access request being completely serviced, intervening, using said coherence transformer, to prevent said memory module from servicing said third memory access request.

17. The method of claim 16 further comprising:

if said second memory access request is completely serviced, unallocating said temporary buffer to enable said temporary buffer to be used in temporarily tracking another memory block associated with another memory access request by said external device.

18. The method of claim 10 further comprising:

receiving, at a coherence transformer coupled to said common bus, a third memory access request for a second memory block from said external device;

obtaining said second memory block, using said coherence transformer, from said common bus;

modifying, using said coherence transformer, a second Mtag associated with said second memory block in said memory module at said computer node to reflect that said external device is caching a valid copy of said second memory block; and

sending said valid copy of said second memory block from said coherence transformer to said external device.

19. The method of claim 18 wherein said third memory access request from said external device represents a request for an exclusive copy of said first memory block and said step of modifying said second Mtag includes a step of changing said second Mtag in said memory module to an invalid state.

20. The method of claim 19 further comprising a step of invalidating all valid copies of said second memory block at said computer node.

21. An apparatus for facilitating the sharing of memory blocks between a computer node and an external device, comprising:

receiver logic configured for coupling with a common bus of said computer node, said receiver logic being configured to receive, when coupled to said common bus, memory access requests specific to said apparatus on said common bus; and

a protocol transformer logic coupled to said receiver logic for enabling said apparatus, when coupled to said external device, to communicate with said external device using a protocol suitable for communicating with said external device, whereby said sharing of said memory blocks is facilitated irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, and wherein each of said memory blocks has a local physical address at a memory module of said computer node and an associated Mtag for tracking a state associated with said each of said memory blocks, including an exclusive state for indicating that said each of said memory blocks is exclusive to said computer node, a shared state for indicating that said each of said memory blocks is shared by said computer node with said external device, and an invalid state for indicating that said each of said memory blocks is invalid in said computer node.

22. The apparatus of claim 21 wherein said receiver logic includes a temporary buffer for temporarily storing an address and a state of a first memory block requested by a first memory access request issued by said external device, said temporary buffer being unallocated after an Mtag state of said first memory block is changed in said memory module to reflect that said first memory block is cached by said external device.

23. The apparatus of claim 22 further including:

monitoring logic for monitoring memory access requests on said common bus;

logic configured to respond to said first memory access request of said memory access requests on said common bus, said first memory access request pertaining to said first memory block while said address of said first memory block is temporarily stored in said buffer.

24. The apparatus of claim 21 wherein said receiver logic performs the operations of:

receiving a first memory access request from said external device, said first memory access request pertaining to one of said memory blocks;

issuing a second memory access request, responsive to said first memory access request, to said common bus to request a copy of said one of said memory blocks;

receiving said copy of said one of said memory blocks from said common bus;

writing a first Mtag state to said memory module to reflect the fact that said one of said memory blocks is cached by said external device; and

sending said copy of said one of said memory blocks received from said common bus to said external device.

25. The apparatus of claim 24 wherein said first memory access request is a request for an exclusive copy of said one of said memory blocks, said first Mtag state representing said exclusive state.

26. The apparatus of claim 24 wherein said first memory access request is a request for a shared copy of said one of said memory blocks, said first Mtag state representing said shared state.

27. The apparatus of claim 21 wherein said receiver logic operates to obtain a copy of a first memory block from said external device, said copy of said first memory block representing a copy requested by one of said memory access requests specific to said apparatus.

28. The apparatus of claim 27 wherein said receiver logic operates to send said copy of said first memory block obtained from said external device to said common bus, thereby enabling a progenitor of said one of said memory access requests specific to said apparatus to obtain said copy of said first memory block.

29. A computer system having a computer node and an external device, said computer node having memory blocks with local physical addresses at said computer node, said computer system enabling said computer node and said external device to share said memory blocks, comprising:

receiver logic configured for coupling with a common bus of said computer node, said receiver logic being configured to receive, when coupled to said common bus, memory access requests specific to said computer system on said common bus; and

a protocol transformer logic coupled to said receiver logic for enabling said computer system, when coupled to said external device, to communicate with said external device using a protocol suitable for communicating with said external device, whereby said sharing of said memory blocks is facilitated irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, and wherein each of said memory blocks has a local physical address at a memory module of said computer node and an associated Mtag for tracking a state associated with said each of said memory blocks, including an exclusive state for indicating that said each of said memory blocks is exclusive to said computer node, a shared state for indicating that said each of said memory blocks is shared by said computer node with said external device, and an invalid state for indicating that said each of said memory blocks is invalid in said computer node.

30. The computer system of claim 29 wherein said receiver logic includes a temporary buffer for temporarily storing an address and a state of a first memory block requested by a first memory access request issued by said external device, said temporary buffer being unallocated after an Mtag state of said first memory block is changed in said memory module to reflect that said first memory block is cached by said external device.

31. The computer system of claim 30 further including:

monitoring logic for monitoring memory access requests on said common bus; and

logic configured to respond to said first memory access request of said memory access requests on said common bus, said first memory access request pertaining to said first memory block while said address of said first memory block is temporarily stored in said buffer.

32. The computer system of claim 29 wherein said receiver logic performs the operations of:

receiving a first memory access request from said external device, said first memory access request pertaining to one of said memory blocks;

issuing a second memory access request, responsive to said first memory access request, to said common bus to request a copy of said one of said memory blocks;

receiving said copy of said one of said memory blocks from said common bus;

writing a first Mtag state to said memory module to reflect the fact that said one of said memory blocks is cached by said external device; and

sending said copy of said one of said memory blocks received from said common bus to said external device.

33. The computer system of claim 32 wherein said first memory access request is a request for an exclusive copy of said one of said memory blocks, said first Mtag state representing said exclusive state.

34. The computer system of claim 32 wherein said first memory access request is a request for a shared copy of said one of said memory blocks, said first Mtag state representing said shared state.

35. The computer system of claim 29 wherein said receiver logic operates to obtain a copy of a first memory block from said external device, said copy of said first memory block representing a copy requested by one of said memory access requests specific to said computer system.

36. The computer system of claim 35 wherein said receiver logic operates to send said copy of said first memory block obtained from said external device to said common bus, thereby enabling a progenitor of said one of said memory access requests specific to said computer system to obtain said copy of said first memory block.