Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains
First Claim
1. In a computer system having a computer node which has a common bus, a method for enabling an external device to share memory blocks having local physical addresses in a memory module at said computer node irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, each of said memory blocks having an associated Mtag for tracking a state associated with said each of said memory blocks, including a state for indicating that said each of said memory blocks is exclusive to said computer node, a state for indicating that said each of said memory blocks is shared by said computer node with said external device, and a state for indicating that said each of said memory blocks is invalid in said computer node, said method comprising:
- receiving, at a coherence transformer coupled to said common bus, a first memory access request for a first memory block from said external device;
obtaining said first memory block, using said coherence transformer, from said common bus;
modifying, using said coherence transformer, a first Mtag associated with said first memory block in said memory module at said computer node to reflect that said external device is caching a valid copy of said first memory block; and
sending said valid copy of said first memory block from said coherence transformer to said external device.
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Accused Products
Abstract
An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus. There is further included a protocol transformer logic coupled to the receiver logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device irrespective of the external device speed or protoco.
42 Citations
36 Claims
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1. In a computer system having a computer node which has a common bus, a method for enabling an external device to share memory blocks having local physical addresses in a memory module at said computer node irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, each of said memory blocks having an associated Mtag for tracking a state associated with said each of said memory blocks, including a state for indicating that said each of said memory blocks is exclusive to said computer node, a state for indicating that said each of said memory blocks is shared by said computer node with said external device, and a state for indicating that said each of said memory blocks is invalid in said computer node, said method comprising:
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receiving, at a coherence transformer coupled to said common bus, a first memory access request for a first memory block from said external device; obtaining said first memory block, using said coherence transformer, from said common bus; modifying, using said coherence transformer, a first Mtag associated with said first memory block in said memory module at said computer node to reflect that said external device is caching a valid copy of said first memory block; and sending said valid copy of said first memory block from said coherence transformer to said external device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a computer system having a computer node which has a common bus, a method for enabling an external device to share memory blocks having local physical addresses in a memory module at said computer node through a coherence transformer coupled to a common bus of said computer node irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, each of said memory blocks having an associated Mtag for tracking a state associated with said each of said memory blocks, including a state for indicating that said each of said memory blocks is exclusive to said computer node, a state for indicating that said each of said memory blocks is shared by said computer node with said external device, and a state for indicating that said each of said memory blocks is invalid in said computer node, said method comprising:
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receiving, at said memory module via said common bus, a first memory access request for a valid copy of a first memory block of said memory blocks from a progenitor of said first memory access request, said progenitor being an entity different from said coherence transformer; responding to said first memory access request by sending a first copy of said first memory block, along with a first Mtag corresponding to said first memory block, from said memory module to said progenitor of said first memory access request; examining, using said progenitor of said first memory access request, said first Mtag state; and if said first Mtag state is invalid, issuing a second memory access request pertaining to said first memory block from said progenitor of said first memory access request to request said coherence transformer to service said second memory access request, thereby enabling said progenitor of said first memory access request to obtain said valid copy of said first memory block. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An apparatus for facilitating the sharing of memory blocks between a computer node and an external device, comprising:
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receiver logic configured for coupling with a common bus of said computer node, said receiver logic being configured to receive, when coupled to said common bus, memory access requests specific to said apparatus on said common bus; and a protocol transformer logic coupled to said receiver logic for enabling said apparatus, when coupled to said external device, to communicate with said external device using a protocol suitable for communicating with said external device, whereby said sharing of said memory blocks is facilitated irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, and wherein each of said memory blocks has a local physical address at a memory module of said computer node and an associated Mtag for tracking a state associated with said each of said memory blocks, including an exclusive state for indicating that said each of said memory blocks is exclusive to said computer node, a shared state for indicating that said each of said memory blocks is shared by said computer node with said external device, and an invalid state for indicating that said each of said memory blocks is invalid in said computer node. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A computer system having a computer node and an external device, said computer node having memory blocks with local physical addresses at said computer node, said computer system enabling said computer node and said external device to share said memory blocks, comprising:
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receiver logic configured for coupling with a common bus of said computer node, said receiver logic being configured to receive, when coupled to said common bus, memory access requests specific to said computer system on said common bus; and a protocol transformer logic coupled to said receiver logic for enabling said computer system, when coupled to said external device, to communicate with said external device using a protocol suitable for communicating with said external device, whereby said sharing of said memory blocks is facilitated irrespective whether said external device and said common bus both employ a common protocol and irrespective whether said external device and said common bus both operate at the same speed, and wherein each of said memory blocks has a local physical address at a memory module of said computer node and an associated Mtag for tracking a state associated with said each of said memory blocks, including an exclusive state for indicating that said each of said memory blocks is exclusive to said computer node, a shared state for indicating that said each of said memory blocks is shared by said computer node with said external device, and an invalid state for indicating that said each of said memory blocks is invalid in said computer node. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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Specification