Data buffering system including buffer memory shared between channel data groups whereas buffer memory is divided into memory areas for storing different types of channel data groups

• US 5,941,961 A
• Filed: 08/13/1997
• Issued: 08/24/1999
• Est. Priority Date: 08/16/1996
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nakahara, Masanao
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US08/910,119
• Time in Patent Office: 741 Days
• Field of Search: 395/872, 395/873, 395/874, 395/876, 711/170, 711/147, 711/148, 711/153
• US Class Current: 710/52
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A plurality of channel data groups and a coupling data group are supplied to a data input port of a data buffering apparatus so as to be temporarily stored in a buffering memory having a first memory area assigned to a non-coupled channel data group, a second memory area assigned to a coupled channel data group and a third memory area assigned to the coupling data group, and the data buffering apparatus outputs the channel data group from the first memory area or the channel data group and the coupling data group from the second and third memory areas before the next channel data group arrives at the data input port so as to decrease the memory areas of the buffer memory.

Claims

1. A data buffering apparatus for temporarily storing a plurality of channel data groups each having a plurality of channel data components representative of pieces of data information and a coupling channel data group having a coupling data component representative of one of said pieces of data information shared between at least two of said plurality of channel data groups and at least one control data component representative of a piece of control data information used for said coupling data component, comprising:

a data input port for successively receiving said plurality of channel data groups and said coupling data group;

a buffer memory having

a first memory area assigned to one of said plurality of channel data groups without said coupling data component,

a second memory area assigned to another of said plurality of channel data groups having channel data components selected from said plurality of channel data components in such a manner as to delete said coupling data component from said plurality of channel data components, and

a third memory area assigned to said coupling data group; and

a data controlling means connected between said data input port and said buffer memory, checking each of said plurality of channel data groups to see whether or not said coupling data component is incorporated therein so as to write said each of said plurality of channel data group into one of said first memory area and said second memory area, and writing said coupling data group into said third memory area,

said data controlling means overwriting yet another of said plurality of channel data groups into said first area already stored said one of said plurality of channel data groups when said yet another of said plurality of channel data groups does not contain said coupling data component,

said data controlling means overwriting still another of said plurality of channel data groups into said second memory area already stored said another of said plurality of channel data groups when said still another of said plurality of channel data groups contains said coupling data component.

2. The data buffering apparatus as set forth in claim 1, in which said second memory area is contiguous to said third memory area, and a boundary between said second memory area and said third memory area is variable depending upon the combination of said another of said plurality of channel data groups and said coupling data group.

3. The data buffering apparatus as set forth in claim 2, in which said second memory area and said third memory area are defied by a first address to a second address and said second address to a third address, respectively, and said another of said plurality of channel data groups and said coupling data group are written from said first address toward said second address and from said third address toward said second address, respectively.

4. The data buffering apparatus as set forth in claim 3, in which said first memory area is defined by a fourth address to a fifth address, and the length between said first address and said third address is equal to the length between said fourth address and said fifth address.

5. The data buffering apparatus as set forth in claim 1, in which at least one of said plurality of channel data components has been compressed before arriving at said data input port, and said data controlling means includes a data expanding circuit connected to said data input port so as to expand said one of said plurality of channel data components.

6. The data buffering apparatus as set forth in claim 5, in which said data controlling mean further includes a controlling circuit connected to said data input port and checking each of said plurality of channel data groups and said coupling data group to see whether or not said one of said plurality of channel data components already compressed is incorporated therein, and said controlling circuit supplies a first control signal representative of existence of said one of said plurality of channel data components already compressed to said data expanding circuit.

7. The data buffering apparatus as set forth in claim 4, in which said data controlling means includes a controlling circuit discriminating each of said one of said plurality of channel data groups, said another of said plurality of channel data groups and said coupling data group from the others so as to cause an address generating circuit to supply an address signal representative of an address between said first address and said third address or between said fourth address and said fifth address to said buffer memory.

8. A method of controlling a data buffering apparatus for temporarily storing a plurality of channel data groups each having a plurality of channel data components representative of pieces of data information and a coupling channel data group having a coupling data component representative of one of said pieces of data information shared between at least two of said plurality of channel data groups and at least one control data component representative of a piece of control data information used for said coupling data component, comprising the steps of:

a) discriminating one of said plurality of channel data groups without said coupling data component, another of said plurality of channel data groups with said coupling data component and said coupling data group from the others;

b) writing said one of said plurality of channel data groups into a first memory area assigned to a channel data group without said coupling data component, a second memory area assigned to a channel data group with said coupling data component or a third memory area assigned to said coupling data group depending upon the discrimination at step a);

c) repeating said steps a) and b) until said one of said plurality of channel data groups is written into said first memory area or said one of said channel data groups and said coupling data group are written into said second memory area and said third memory area, respectively;

d) reading out said one of said plurality of channel data groups from said first memory area or said one of said plurality of channel data groups and said coupling data group from said second memory area and said third memory area; and

e) repeating said step a); and

f) overwriting said one of said plurality of channel data groups into said first memory area, said second memory area or said third memory area depending upon the discrimination at step e).