Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device

• US 5,941,968 A
• Filed: 04/14/1997
• Issued: 08/24/1999
• Est. Priority Date: 04/14/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mergard, James Oliver, Wakeland, Carl K., Quimby, Michael S.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): KIM, HAROLD J
• Application Number:
  US08/837,120
• Time in Patent Office: 862 Days
• Field of Search: 395/308, 395/306, 395/872, 711/146, 710/128, 710/126, 710/52
• US Class Current: 710/308
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A computer system is provided including a CPU, a graphics controller, system memory, data steering logic, a DMA controller and arbitration logic. The graphics controller and system memory are coupled to a high-speed data bus. Data accessed by the CPU, the DMA controller and the graphics controller is all stored in the system memory. The data steering logic is also coupled to the high-speed data bus and to a low-speed data bus, and to the CPU. The data steering logic is configured to selectively couple the CPU to either the high-speed data bus or the low-speed data bus, thereby accommodating data transfers between the CPU and a bus device connected to the slow-speed data bus concurrent with data transfers between the graphics controller and the system memory. The data steering logic may also accommodate data transfers by the DMA controller on the slow-speed data bus concurrent with graphics controller data transfers. The arbitration logic arbitrates for access to the system memory between the CPU, DMA controller and graphics controller. In an alternative mode, the data steering logic accommodates data transfers between the CPU and the system memory over both the high-speed and slow-speed buses as a single double width high speed bus. The CPU, graphics controller, DMA controller, data steering logic and arbitration logic as described above may all be included within a single integrated circuit device along with various PC compatibility cores, thus achieving a low-cost, low-space system without sacrificing overall performance.

Claims

1. A computer system, comprising:

a central processing unit (CPU);

a graphics controller coupled to a first data bus;

system memory coupled to said first data bus, wherein data accessed by said CPU and data accessed by said graphics controller are both stored in said system memory;

data steering logic coupled to said first data bus, to a second data bus, and to said CPU, wherein said data steering logic is configured to selectively couple said CPU to a data bus selected from said first data bus and said second data bus, and wherein said data steering logic accommodates data transfers between said CPU and a device connected to said second data bus concurrent with data transfers between said graphics controller and said system memory, wherein said second data bus comprises an expansion data bus and said device comprises an expansion bus device; and

memory arbitration logic coupled to said graphics controller and said CPU, wherein said memory arbitration logic is configured to arbitrate for access to said system memory.

2. The computer system as recited in claim 1, further comprising a direct memory access (DMA) controller operably coupled to said memory arbitration logic, wherein said memory arbitration logic and said data steering logic are configured to accommodate said DMA controller accessing said device on said second data bus concurrent with said graphics controller accessing said system memory.

3. The computer system as recited in claim 2, further comprising system arbitration logic coupled to said CPU and coupled to said DMA controller, wherein said system arbitration logic indicates to said memory arbitration logic a winner of arbitration between said CPU and said DMA controller, and wherein said memory arbitration logic arbitrates between said winner and said graphics controller for access to said system memory.

4. The computer system as recited in claim 3, wherein said system arbitration logic is configured to arbitrate between said CPU and said DMA controller with said CPU as default winner.

5. The computer system as recited in claim 3, wherein said memory arbitration logic is configured for said graphics controller to have arbitration priority over said winner.

6. The computer system as recited in claim 3, wherein said CPU comprises a cache memory configured to accommodate data transfers between said CPU and said cache memory concurrent with data transfers between said graphics controller and said system memory.

7. The computer system as recited in claim 6, wherein said system arbitration logic is configured to accommodate snoops of said cache memory during DMA controller accesses of said system memory.

8. The computer system as recited in claim 1, wherein said CPU comprises a cache memory configured to accommodate data transfers between said CPU and said cache memory concurrent with data transfers between said graphics controller and said system memory.

9. The computer system as recited in claim 1, wherein said graphics controller comprises a FIFO memory configured to accommodate data transfers between said graphics controller and said FIFO memory concurrent with data transfers between said CPU and said system memory.

10. The computer system as recited in claim 1, wherein said first data bus accommodates a higher data transfer bandwidth than said second data bus.

11. An integrated circuit device, comprising:

a central processing unit (CPU);

a graphics controller coupled to a first data bus, wherein said first data bus is configured to couple to a system memory external to the integrated circuit, and wherein data accessed by said CPU and data accessed by said graphics controller are both stored in said system memory;

data steering logic coupled to said first data bus, to a second data bus, and to said CPU, wherein said data steering logic is configured to selectively couple said CPU to a data bus selected from said first data bus and said second data bus, and wherein said data steering logic accommodates data transfers between said CPU and an external device coupled to said second data bus concurrent with data transfers between said graphics controller and said system memory, wherein said second data bus comprises an expansion data bus and said device comprises an expansion bus device; and

memory arbitration logic coupled to said graphics controller and coupled to said CPU, wherein said memory arbitration logic is configured to arbitrate for access to said system memory.

12. The integrated circuit device as recited in claim 11, further comprising a direct memory access (DMA) controller operably coupled to said memory arbitration logic, wherein said memory arbitration logic and said data steering logic are configured to accommodate said DMA controller accessing said external device on said second data bus concurrent with said graphics controller accessing said system memory.

13. The integrated circuit device as recited in claim 12, further comprising system arbitration logic coupled to said CPU and coupled to said DMA controller, wherein said system arbitration logic indicates to said memory arbitration logic a winner of arbitration between said CPU and said DMA controller, and wherein said memory arbitration logic arbitrates between said winner and said graphics controller for access to said system memory.

14. The integrated circuit device as recited in claim 13, wherein said system arbitration logic is configured to arbitrate between said CPU and said DMA controller with said CPU as default winner.

15. The integrated circuit device as recited in claim 13, wherein said memory arbitration logic is configured for said graphics controller to have arbitration priority over said winner.

16. The integrated circuit device as recited in claim 11, wherein said CPU comprises a cache memory configured to accommodate data transfers between said CPU and said cache memory concurrent with data transfers between said graphics controller and said system memory.

17. The integrated circuit device as recited in claim 11, wherein said graphics controller comprises a FIFO memory configured to accommodate data transfers between said graphics controller and said FIFO memory concurrent with data transfers between said CPU and said system memory.

18. The integrated circuit device as recited in claim 11, further comprising a plurality of internal registers coupled to said data steering logic, wherein said data steering logic is further configured to accommodate data transfers between said CPU and said plurality of internal registers concurrent with data transfers between said graphics controller and said system memory.

19. The integrated circuit device as recited in claim 13, further comprising a plurality of internal registers coupled to said data steering logic, wherein said data steering logic is further configured to accommodate data transfers between said CPU and said plurality of internal registers concurrent with data transfers between said graphics controller and said system memory.

20. The integrated circuit device as recited in claim 13, further comprising bus controller logic configured to provide control signals supporting an ISA bus and a PCMCIA bus, wherein said second data bus provides the data signals for said ISA bus and said PCMCIA bus.

21. An integrated circuit, comprising:

data steering logic adapted for coupling to a first data bus, to a second data bus, and to a CPU, wherein said data steering logic is configured in a first mode to selectively couple said CPU to a data bus selected from said first data bus and said second data bus, and wherein said data steering logic accommodates data transfers between said CPU and a second device connected to said second data bus concurrent with data transfers between a first device and a system memory, wherein said first device and said system memory are connected to said first data bus, and wherein in said first mode said second data bus comprises an expansion data bus and said device comprises an expansion bus device; and

memory arbitration logic adapted in said first mode for coupling to said first device and said CPU, wherein said memory arbitration logic is configured to arbitrate for access to said system memory.

22. The integrated circuit as recited in claim 21, further comprising a direct memory access (DMA) controller coupled to said memory arbitration logic, wherein said memory arbitration logic and said data steering logic are configured in said first mode to accommodate said DMA controller accessing said second device concurrent with said first device accessing said system memory.

23. The integrated circuit as recited in claim 21, wherein said data steering logic is configured in a second mode to couple said CPU to said first data bus and to said second data bus, wherein said data steering logic accommodates data transfers between said CPU and said system memory, wherein said system memory is connected to said first data bus and to said second data bus.

24. The integrated circuit as recited in claim 23, further comprising a direct memory access (DMA) controller coupled to said memory arbitration logic, wherein said memory arbitration logic is configured in said second mode to arbitrate between said CPU and said DMA controller for access to said system memory.

25. The integrated circuit as recited in claim 23, wherein said data steering logic accommodates data transfers having a first data width between said CPU and said system memory, and wherein said data steering logic accommodates data transfers having a second data width between said CPU and said system memory, wherein said second data width is twice said first data width.

26. A method for improving bus concurrency in a computer system, comprising:

providing a central processing unit (CPU);

providing a graphics controller coupled to a first data bus;

providing a unified system memory coupled to said first data bus;

providing an expansion bus device coupled to an expansion data bus;

steering data between said CPU and said bus device, wherein data transfers are accommodated between said CPU and said expansion bus device concurrent with data transfers between said graphics controller and said unified system memory; and

arbitrating between said CPU and said graphics controller for access to said unified system memory.