Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate
First Claim
Patent Images
1. An integrated circuit comprising:
- (a) a substrate;
(b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ
1) and a third oxide thickness different from the second by (Δ
2), wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 80 Å
gate oxide layer and, the third oxide thicknesses is an approximately 90 Å
tunnel oxide layer.
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Abstract
An integrated circuit ("IC") having three different oxide layer thicknesses and a process for manufacturing the IC using a single oxide growth step is provided. A first region is formed on a substrate surface with oxidation enhancing properties. A second region is formed on the substrate surface with a dose of nitrogen that retards oxidation. An oxide layer is grown from the first and the second regions and a third region of the substrate such that the first, second, and third regions yield a first oxide layer for the capacitor, a second oxide layer for the read transistor and a third oxide layer for the write transistor.
71 Citations
6 Claims
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1. An integrated circuit comprising:
-
(a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ
1) and a third oxide thickness different from the second by (Δ
2), wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 80 Å
gate oxide layer and, the third oxide thicknesses is an approximately 90 Å
tunnel oxide layer.
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2. An integrated circuit comprising:
-
(a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ
1) and a third oxide thickness different from the second by (Δ
2), wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 70 Å
gate oxide layer and, the third oxide thickness is an approximately 90 Å
tunnel oxide layer.
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3. An integrated circuit comprising:
-
(a) a substrate; (b) an oxide layer where the oxide layer includes a first oxide thickness, a second oxide thickness different from the first by (Δ
1) and a third oxide thickness different from the second by (Δ
2), wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 50 Å
gate oxide layer and, the third oxide thickness is an approximately 90 Å
tunnel oxide layer.
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4. A non-volatile memory cell on a silicon wafer substrate, comprising:
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(a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; (b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and
,(c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 80 Å
gate oxide layer and, the third oxide thickness is an approximately 90 Å
tunnel oxide layer.
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5. A non-volatile memory cell on a silicon wafer substrate, comprising:
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(a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; (b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and
,(c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 70 Å
gate oxide layer and, the third oxide thickness is an approximately 90 Å
tunnel oxide layer.
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6. A non-volatile memory cell on a silicon wafer substrate, comprising:
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(a) a first transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a first oxide thickness; b) a second transistor having a drain, source, channel and control gate, the control gate being separated from the channel by a gate oxide layer having a second oxide thickness; and
,(c) a tunnel capacitor having a tunnel oxide layer having a third oxide thickness, wherein the first oxide thickness is an approximately 150 Å
gate oxide layer, the second oxide thickness is an approximately 50 Å
gate oxide layer and, the third oxide thickness is an approximately 90 Å
tunnel oxide layer.
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Specification
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Current AssigneeLattice Semiconductor Corporation
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsBarsan, Radu M., Mehta, Sunil, Li, Xiao-Yu
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Primary Examiner(s)WALLACE, VALENCIA MARTIN
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Application NumberUS08/689,523Time in Patent Office1,110 DaysField of Search257/314, 257/315, 257/316, 257/318, 257/321, 438/258, 438/259, 438/264, 365/185.1, 365/185.04US Class Current257/321CPC Class CodesH10B 41/30 characterised by the memory...H10B 41/60 the control gate being a do...H10B 69/00 Erasable-and-programmable R...
