Display panel driving circuit

• US 5,943,030 A
• Filed: 11/25/1996
• Issued: 08/24/1999
• Est. Priority Date: 11/24/1995
• Status: Expired due to Term

• Current Assignee: Vista Peak Ventures LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: NEC Corporation
• Inventors: Minamibayashi, Seisaku
• Primary Examiner(s): Chow, Dennis-Doon
• Assistant Examiner(s): AWAD, AMR A
• Application Number:
  US08/756,255
• Time in Patent Office: 1,002 Days
• Field of Search: 345/41, 345/42, 345/60, 345/61, 345/62, 345/76, 315/169.3
• US Class Current: 345/60
• CPC Class Codes: G09G 3/296 Driving circuits for producing the waveforms applied to the driving electrodes
• CPC Class Codes: G09G 3/2965 using inductors for energy recovery

Abstract

A display panel driving circuit includes a plurality of elementary driver circuits each provided for each one of drive electrodes, an electric power recovery common line, an electric power release common line, first and second coils having one end thereof connected to the electric power recovery common line and the electric power release common line, respectively, and a capacitor having one end connected in common to the other end of the first and second coils. Each of the elementary driver circuits includes a first switch on-off controlled to recover a recovery current from a corresponding drive electrode to an electric power recovery line, a second switch on-off controlled to selectively connect the corresponding drive electrode to a low potential power supply line, a third switch on-off controlled to supplying a recovered electric current from an electric power release line to the corresponding drive electrode, and a fourth on-off controlled to selectively connect a high potential power supply line to the corresponding drive electrode. The electric power recovery common line is connected in common to the electric power recovery line of all the elementary driver circuits, and the electric power release common line is connected in common to the electric power release line of all the elementary driver circuits. The first to fourth switches of each of the elementary driver circuits are so controlled that each of the elementary driver circuits can perform the electric power recovery operation and the electric power release operation simultaneously in parallel to those of the other elementary driver circuits. Thus, the electric power recovery/release can be carried out not only in the display cell sustain discharge driving period but also in the display data writing period.

Claims

1. A circuit for driving a display panel which includes a number of display cells located in the form of a matrix and comprises a plurality of drive electrodes which are independent of one another and which constitute a capacitive load, said driving circuit being configured to drive each of said plurality of drive electrodes by an AC drive pulse and to recover a reactive electric power attributable to said capacitive load so as to supply said recovered electric power together with a next drive pulse, for the purpose of improving a driving efficiency, said driving circuit comprising:

a plurality of elementary driver circuits each provided for each one of said drive electrodes, each including;

a first switch connected between a corresponding one of said drive electrodes and an electric power recovery line, and on-off controlled to recover from said corresponding drive electrode a recovery current corresponding to said reactive electric power;

a second switch connected between said corresponding drive electrode and a low potential power supply line, and on-off controlled to selectively connect said low potential power supply line;

a third switch connected between said corresponding drive electrode and an electric power release line, and on-off controlled to supplying a recovered electric current to said corresponding drive electrode; and

a fourth switch connected between said corresponding drive electrode and a high potential power supply line, and on-off controlled to selectively connect said high potential power supply line to said corresponding drive electrode;

a first common line connected in common to said electric power recovery line of said plurality of elementary driver circuits;

a second common line connected in common to said electric power release line of said plurality of elementary driver circuits;

first and second inductors having one end thereof connected to said first and second common lines respectively;

a first capacitor having one end connected in common to the other end of said first and second inductors and the other end connected to a predetermined potential; and

a driver control circuit for supplying switch control signals to said first to fourth switches of each of said plurality of elementary driver circuits;

wherein said driver control circuit comprises;

a first register composed of an "s"-stage shift register serially receiving a driving data signal in synchronism with a clock signal, for output a first register signal of "s" bits in parallel, where "s" is integer larger than one;

a second register composed of"s" latch circuits, for latching, in parallel, said "s" bits of said first register signal from said first register in response to a latch control signal, and for outputting a second register signal of"s" bits;

"s" exclusive-OR gates each receiving a pair of mutually corresponding bits of said first and second register signals, for detecting a logical transition in said driving data signal, to generate a transition detection signal;

"s" logic circuits each receiving recovery/release control signal and said transition detection signal of a corresponding exclusive-OR gate of said "s" exclusive-OR gates, for generating a first control pulse; and

"s" decoders each receiving said first control pulse of a corresponding logic circuit of said "s" logic circuits and a corresponding bit of said second register signal, for generating first to fourth on-off control signals for said first to fourth switches of a corresponding elementary driver circuit of said elementary driver circuits of said driver control circuit.

2. A display panel driving circuit claimed in claim 1 wherein, during a period in which said recovery/release control signal is at an active level, said driver control circuit prevents said first register signal from being latched to said second register, and after an elapse of a predetermined time period from execution of each of the electric power recovery operation and the electric power release operation, said driver control circuit causes said second register to latch said first register signal, so that when no logical level transition occurs in said drive data signal, neither the electric power recovery operation or the electric power release operation is carried out.

3. A display panel driving circuit claimed in claim 1 wherein wherein said driver control circuit further includes "s" second exclusive-OR gates each receiving a polarity control signal and a corresponding bit of said second register signal, for generating a second control pulse, and each of said "s" decoders receives said first control pulse of said corresponding logic circuit of said "s" logic circuits and said second control pulse of a corresponding second exclusive-OR gate of said "s" second exclusive-OR gates, so that all of said elementary driver circuits are caused to carry out the same operation in parallel by controlling said polarity control signal.

4. A circuit for driving a display panel which includes a number of display cells located in the form of a matrix and comprises a plurality of drive electrodes which are independent of one another and which constitute a capacitive load, said driving circuit being configured to drive each of said plurality of drive electrodes by an AC drive pulse and to recover a reactive electric power attributable to said capacitive load so as to supply said recovered electric power together with a next drive pulse for the purpose of improving a driving efficiency, said driving circuit comprising:

a plurality of elementary driver circuits each provided for each one of said drive electrodes each including;

a first switch connected between a corresponding one of said drive electrodes and an electric power recovery line, and on-off controlled to recover from said corresponding drive electrode a recovery current corresponding to said reactive electric power;

a second switch connected between said corresponding drive electrode and a low potential power supply line, and on-off controlled to selectively connect said low potential power supply line;

a third switch connected between said corresponding drive electrode and an electric power release line, and on-off controlled to supplying a recovered electric current to said corresponding drive electrode; and

a fourth switch connected between said corresponding drive electrode and a high potential power supply line, and on-off controlled to selectively connect said high potential power supply line to said corresponding drive electrode;

a first common line connected in common to said electric power recovery line of said plurality of elementary driver circuits;

a second common line connected in common to said electric power release line of said plurality of elementary driver circuits;

first and second inductors having one end thereof connected to said first and second common lines, respectively;

a first capacitor having one end connected in common to the other end of said first and second inductors and the other end connected to a predetermined potential;

a driver control circuit for supplying switch control signals to said first to fourth switches of each of said plurality of elementary driver circuits;

wherein said display panel is an AC drive type plasma display panel which includes a number of display cells located in the form of a matrix, a plurality of mutually independent data electrodes arranged along a plurality of columns of said matrix of said display cells, and a plurality of mutually independent scan electrodes arranged along a plurality of rows of said matrix of said display cells, and wherein the display panel driving circuit includes a data electrode drive circuit for supplying a data drive pulse to each of said data electrodes and a scan electrode drive circuit for supplying a scan drive pulse to each of said scan electrodes, said data electrode drive circuit including;

said elementary drive circuits of a first number, each provided for each one of said data electrodes for responding to first driver control signals to supply a data electrode drive voltage to a corresponding data electrode independently of the other data electrodes and carry out an electric power recovery and release operation for said corresponding data electrode independently of the other data electrodes;

said first common line and said second common line connected in common to said electric power recovery line and said electric power release line of said elementary driver circuits respectively;

said first and second inductors having one end thereof connected to said first and said common lines, respectively;

said first capacitor having one end connected in common to the other end of said first and second inductors and the other end connected to said predetermined potential; and

a first driver control circuit for generating said first driver control signals in response to an input data signal,

said scan electrode drive circuit including;

elementary driver circuits of a second number, each provided for each one of said scan electrodes, for responding to second driver control signals to supply a scan electrode drive voltage to a corresponding scan electrode independently of the other scan electrodes, and carry out the electric power recovery and release operation for said corresponding scan electrode;

independently of the other scan electrodes;

a third common line and a fourth common line connected in common to said electric power recovery line and said electric power release line of said elementary driver circuits, respectively, of said scan electrode drive circuit;

third and fifth inductors each having one end thereof connected to said third common line;

fourth and sixth inductors each having one end thereof connected to said fourth common line;

a second capacitor having one end connected in common to the other end of said fifth and sixth inductors;

a third capacitor having one end connected in common to the other end of said third and fourth inductors;

a first switch having one end connected to the other end of said second capacitor and the other end connected to said predetermined potential; and

a second switch having one end connected to the other end of said third capacitor and the other end connected to said predetermined potential; and

a second driver control circuit for generating said second driver control signals in response to an input scan signal, said second driver control circuit alternatively closing said second switch and said third switch in accordance with a scan electrode driving condition;

wherein said second driver control circuit comprises;

a first register composed of an "s"-stage shift register serially receiving a scan data signal in synchronism with a clock signal, for output a first register signal of "s" bits in parallel, where "s" is integer larger than one;

a second register composed of"s" latch circuits, for latching, in parallel, said "s" bits of said first register signal from said first register in response to a latch control signal, and for outputting a second register signal of "s" bits;

"s" exclusive-OR gates each receiving a pair of mutually corresponding bits of said first and second register signals, for detecting a logical transition in said scan data signal, to generate a transition detection signal;

"s" logic circuits each receiving a recovery/release control signal and said transition detection signal of a corresponding exclusive-OR gate of said "s" exclusive-OR gates, for generating a first control pulse; and

"s" decoders each receiving said first control pulse of a corresponding logic circuit of said "s" logic circuits and a corresponding bit of said second register signal, for generating first to fourth on-off control signals for said first to fourth switches of a corresponding elementary driver circuit of said elementary driver circuits of said driver control circuit.

5. A display panel driving circuit claimed in claim 4 wherein wherein said second driver control circuit further includes "s" second exclusive-OR gates each receiving a polarity control signal and a corresponding bit of said second register signal, for generating a second control pulse, and each of said "s" decoders receives said first control pulse of said corresponding logic circuit of said "s" logic circuits and said second control pulse of a corresponding second exclusive-OR gate of said "s" second exclusive-OR gates, so that all of said elementary driver circuits are caused to carry out the same operation in parallel by controlling said polarity control signal.

6. A display panel driving circuit claimed in claim 4, wherein said first driver control includes:

a first register composed of an "s"-stage shift register serially receiving a driving data signal in synchronism with a clock signal, for output a first register signal of"s" bits in parallel, where "s" is integer larger than one;

a second register composed of"s" latch circuits, for latching, in parallel, said "s" bits of said first register signal, and for outputting a second register signal of "s" bits;

"s" exclusive-OR gates each receiving a pair of mutually corresponding bits of said first and second register signals, for detecting a logical transition in said driving data signal, to generate a transition detection signal;

"s" logic circuits each receiving a recovery/release control signal and said transition detection signal of a corresponding exclusive-OR gate of said "s" exclusive -OR gates, for generating a first control pulse; and

"s" decoders each receiving said first control pulse of a corresponding logic circuit of said "s" logic circuits and a corresponding bit of said second register signal, for generating first to fourth on-off control signals for said first to fourth switches of a corresponding elementary driver circuit of said elementary driver circuits of said first driver control circuit.

7. A display panel driving circuit claimed in claim 6 wherein, during a period in which said recovery/release control signal is at an active level, said driver control circuit prevents said first register signal from being latched to said second register, and after an elapse of a predetermined time period from execution of each of the electric power recovery operation and the electric power release operation, said driver control circuit causes said second register to latch said first register signal, so that when no logical level transition occurs in said drive data signal, neither the electric power recovery operation or the electric power release operation is carried out.

8. A display panel driving circuit claimed in claim 7 wherein wherein said first driver control circuit further includes "s" second exclusive-OR gates each receiving a polarity control signal and a corresponding bit of said second register signal, for generating a second control pulse, and each of said "s" decoders receives said first control pulse of said corresponding logic circuit of said "s" logic circuits and said second control pulse of a corresponding second exclusive-OR gate of said "s" second exclusive-OR gates, so that all of said elementary driver circuits are caused to carry out the same operation in parallel by controlling said polarity control signal.