Read only memory
First Claim
Patent Images
1. A read only memory, comprising:
- a multiplicity of conductor tracks respectively disposed in a plurality of conductor track planes including a first conductor track plane and at least one adjacent conductor track plane;
said conductor tracks of said first conductor track plane intersecting said conductor tracks of said at least one adjacent conductor track plane at intersecting regions; and
electrical contacts formed at selected intersecting regions between said conductor tracks of said first conductor track plane and of said at least one adjacent conductor track plane for representing a given logic state at the selected intersecting regions.
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Accused Products
Abstract
The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic "1" or no VIA tunnel contact is provided, so that this intersecting region represents a logic "0". In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.
61 Citations
13 Claims
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1. A read only memory, comprising:
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a multiplicity of conductor tracks respectively disposed in a plurality of conductor track planes including a first conductor track plane and at least one adjacent conductor track plane; said conductor tracks of said first conductor track plane intersecting said conductor tracks of said at least one adjacent conductor track plane at intersecting regions; and electrical contacts formed at selected intersecting regions between said conductor tracks of said first conductor track plane and of said at least one adjacent conductor track plane for representing a given logic state at the selected intersecting regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of operating a read only memory formed with a multiplicity of conductor tracks respectively disposed in a plurality of conductor track planes including a first conductor track plane and at least one adjacent conductor track plane, the conductor tracks of the first conductor track plane intersecting the conductor tracks of the adjacent conductor track plane at intersecting regions and defining memory cells, and electrical contacts formed at selected memory cells between said conductor tracks of said first conductor track plane and of said at least one adjacent conductor track plane for representing a given logic state in the selected memory cell, the method which comprises:
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selecting a given memory cell of the read only memory; applying a first voltage to one conductor track of the selected cell; applying a second voltage to the other conductor track of the selected cell; applying a third voltage to all remaining conductor tracks; and setting the first voltage lower than the third voltage, and the third voltage lower than the second voltage. - View Dependent Claims (12, 13)
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Specification