Method of fabricating 3D multilayer semiconductor circuits

• US 5,943,574 A
• Filed: 02/23/1998
• Issued: 08/24/1999
• Est. Priority Date: 02/23/1998
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Goronkin, Herbert, Tehrani, Saied N., Shiralagi, Kumar
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/027,915
• Time in Patent Office: 547 Days
• Field of Search: 438/300, 438/308, 438/268, 438/269, 438/138, 438/153, 438/151, 438/166, 438/585, 438/212, 438/FOR 176, 438/FOR 192, 148/DIG. 90
• US Class Current: 438/300
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Claims

1. A method of fabricating three-dimensional semiconductor circuits comprising the steps of:

providing a first electrically conductive layer having a doped polysilicon layer positioned thereon and patterned into submicron geometries including first terminals of a first plurality of semiconductor devices, the doped polysilicon layer including grains;

annealing the doped polysilicon layer to expand the grains to avoid grain boundaries within a conductive portion of each of the first terminal semiconductor contacts;

forming insulated gate contacts spaced vertically from the first terminals of the first plurality of semiconductor devices so as to define vertical vias with the conductive portion of each of the first terminal semiconductor contacts providing a lower surface of one each of the vias;

depositing polysilicon including grains on the conductive portion of each of the first terminal semiconductor contacts in the vias to form conduction channels for the first plurality of semiconductor devices, an upper portion of the polysilicon in the vias being doped to form second terminal semiconductor contacts for the first plurality of semiconductor devices;

annealing the polysilicon conduction channels and the polysilicon second terminal semiconductor contacts to expand the grains to avoid grain boundaries within a conductive portion of each of the conduction channels and the second terminal semiconductor contacts; and

depositing and patterning a second electrically conductive layer on the second terminal semiconductor contacts to define second terminals of the first plurality of semiconductor devices.

2. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 1 wherein the first and second electrically conductive layers include one of metal, silicide, and heavily doped semiconductor material.

3. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 1 wherein the step of annealing includes annealing with a laser.

4. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 1 wherein a second plurality of semiconductor devices is fabricated on the first plurality of semiconductor devices by repeating the steps of claim 1 using the second electrically conductive layer of the first plurality of semiconductor devices as the first electrically conductive layer of the second plurality of semiconductor devices.

5. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 1 wherein a second plurality of semiconductor devices is fabricated on the first plurality of semiconductor devices by forming a buffer layer on the first plurality of semiconductor devices and repeating the steps of claim 1 on the buffer layer.

6. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 5 wherein the step of forming the buffer layer includes forming interconnect lines in the buffer layer.

7. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 6 wherein the first plurality of semiconductor devices and the second plurality of semiconductor devices form a three dimensional semiconductor block with contacts to external pads being formed on all facets of the block.

8. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 4 wherein at least one of the second plurality of semiconductor devices cooperates with at least one of the first plurality of semiconductor devices to form a complementary pair of devices.

9. A method of fabricating three-dimensional semiconductor circuits comprising the steps of:

providing a substrate;

depositing a first electrically conductive layer on the substrate;

depositing a doped polysilicon layer having grains on the first electrically conductive layer;

depositing a first insulative layer on the doped polysilicon layer;

patterning the first electrically conductive layer, the doped polysilicon layer, and the first insulative layer into submicron geometries including first terminals of a first plurality of semiconductor devices;

annealing the patterned doped polysilicon layer to expand the grains to avoid grain boundaries within a conductive portion of each of the first terminals of the first plurality of semiconductor devices;

depositing and planarizing a dielectric layer over the submicron geometries;

depositing a polysilicon gate contact layer on the dielectric layer;

depositing a second insulative layer on the polysilicon gate contact layer;

opening vias through the second insulative layer, the polysilicon gate contact layer, and the dielectric layer to the first insulative layer, the vias defining conduction channels for the first plurality of semiconductor devices;

oxidizing exposed portions of the polysilicon gate contact layer within the vias to form a gate dielectric layer;

removing the first insulative layer within the vias to expose the conductive portion of each of the first terminals within each of the vias;

depositing polysilicon with grains on the conductive portion of the first terminal semiconductor contacts in each of the vias to form the conduction channels for the first plurality of semiconductor devices;

doping a top portion of the polysilicon in the vias to form second terminal semiconductor contacts for the first plurality of semiconductor devices;

annealing the polysilicon conduction channels and the polysilicon second terminal semiconductor contacts to expand the grains to avoid grain boundaries within a conductive portion of each of the conduction channels and the second terminal semiconductor contacts; and

depositing and patterning a second electrically conductive layer on the second terminal semiconductor contacts to define second terminals of the first plurality of semiconductor devices.

10. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 9 wherein the first and second electrically conductive layers include one of metal, silicide, and heavily doped semiconductor material.

11. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 9 wherein the step of annealing includes annealing with a laser.

12. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 9 wherein a second plurality of semiconductor devices is fabricated on the first plurality of semiconductor devices by depositing a second doped polysilicon layer with grains on the second electrically conductive layer of the first plurality of semiconductor devices;

depositing a third insulative layer on the second doped polysilicon layer;

patterning the second doped polysilicon layer, and the third insulative layer into submicron geometries including first terminals of the second plurality of semiconductor devices;

annealing the patterned second doped polysilicon layer to expand the grains to avoid grain boundaries within a conductive portion of each of the first terminals of the second plurality of semiconductor devices;

depositing and planarizing a second dielectric layer over the submicron geometries of the second plurality of semiconductor devices;

depositing a second polysilicon gate contact layer on the second dielectric layer;

depositing a fourth insulative layer on the second polysilicon gate contact layer;

opening second vias through the fourth insulative layer, the second polysilicon gate contact layer, and the second dielectric layer to the third insulative layer, the second vias defining conduction channels for the second plurality of semiconductor devices;

oxidizing exposed portions of the second polysilicon gate contact layer within the second vias to form a second gate dielectric layer;

removing the third insulative layer within the second vias to expose the conductive portion of each of the first terminal semiconductor contacts of the second plurality of semiconductor devices within the second vias;

depositing second polysilicon with grains on the conductive portion of the first terminal semiconductor contacts in the second vias to form the conduction channels for the second plurality of semiconductor devices;

doping a top portion of the second polysilicon in the second vias to form second terminal semiconductor contacts for the second plurality of semiconductor devices;

annealing the polysilicon conduction channels and the polysilicon second terminal semiconductor contacts to expand the grains to avoid grain boundaries within a conductive portion of each of the conduction channels and the second terminal semiconductor contacts; and

depositing and patterning a third electrically conductive layer on the second terminal semiconductor contacts of the second plurality of semiconductor devices to define second terminals of the second plurality of semiconductor devices.

13. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 12 wherein at least one of the second plurality of semiconductor devices cooperates with at least one of the first plurality of semiconductor devices to form a complementary pair of devices.

14. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 9 wherein a second plurality of semiconductor devices is fabricated on the first plurality of semiconductor devices by repeating the steps of claim 9, and repeating the step of providing a substrate in the fabrication of the second plurality of semiconductor devices includes forming a buffer layer on the first plurality of semiconductor devices.

15. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 14 wherein the step of forming the buffer layer includes forming interconnect lines between the first and second pluralities of semiconductor devices in the buffer layer.

16. A method of fabricating three-dimensional semiconductor circuits as set forth in claim 15 wherein the first plurality of semiconductor devices and the second plurality of semiconductor devices form a three dimensional semiconductor block with contacts to external pads being formed on all facets of the block.