Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits

• US 5,943,581 A
• Filed: 11/05/1997
• Issued: 08/24/1999
• Est. Priority Date: 11/05/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Lu, Chih-Yuan, Sung, Janmye
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Mao, Daniel H.
• Application Number:
  US08/964,808
• Time in Patent Office: 657 Days
• Field of Search: 438/386-392, 438/243-249
• US Class Current: 438/386
• CPC Class Codes: H10B 12/036 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N⁺ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the device areas aligned over the N⁺ regions. Holes are etched in the epi layer to the N⁺ regions, and a selective wet etch removes the N⁺ doped regions to form cavities. A thin dielectric layer is deposited on the cavity walls, and an N⁺ polysilicon layer is deposited and polished back to form the buried reservoir capacitors. The N⁺ polysilicon in the holes forms the capacitor node contacts for the FETs in the device areas. The array of DRAM cells is completed by growing a gate oxide, depositing and patterning a first polycide layer to form FET gate electrodes on the device areas over the capacitors, thereby providing increased capacitance while reducing the cell area. Lightly doped source/drain (LDD) areas, sidewall spacers and heavily doped source/drain contacts are formed for the FETs. A node strap is formed between one source/drain contact and the node contact to make good electrical contact. An insulating layer is deposited having bit line contact holes, and a second polycide layer is patterned to form the bit lines for the DRAM.

Claims

1. A method of manufacturing an array of buried reservoir capacitors in a silicon substrate for an array of dynamic random access memory (DRAM) cells comprising the steps of:

forming a first photoresist implant mask having an array of openings on said silicon substrate;

forming N⁺ doped regions in said silicon substrate in said openings by ion implantation while said first photoresist implant mask prevents ion implantation elsewhere in said silicon substrate;

removing said first photoresist implant mask;

growing a silicon epitaxy layer on said silicon substrate;

forming an array of P-wells in said silicon epitaxy layer over said N⁺ doped regions by using a patterned second photoresist implant mask;

removing said second photoresist implant mask;

depositing a pad oxide and a silicon nitride layer and forming open areas in said silicon nitride layer in which field oxide isolation regions are required;

forming said field oxide isolation regions surrounding and electrically isolating device areas, said device areas aligned over said N⁺ doped regions;

anisotropically etching holes in said device areas through said silicon nitride layer and said P-wells in said silicon epitaxy layer to said N⁺ doped regions;

isotropically and selectively etching in said holes and thereby removing said N⁺ doped regions, and forming cavities in said silicon substrate;

removing said silicon nitride layer by etching;

depositing an interelectrode dielectric layer on surface of said cavities and on sidewalls of said holes;

depositing a doped polysilicon layer on said interelectrode dielectric layer on said surface of said cavities and filling said holes, said doped polysilicon layer in said holes forming anode electrical contacts for said buried reservoir capacitors;

chemical/mechanically polishing back said doped polysilicon layer to surface of said substrate, thereby completing said array of buried reservoir capacitors.

2. The method of claim 1, wherein said silicon substrate is a single crystal silicon conductively doped N-type with arsenic to a concentration of between about 1.0 E 15 and 1.0 E 18 atoms/cm³.

3. The method of claim 1, wherein said N⁺ doped regions are heavily doped with arsenic (As) to a concentration of between about 1.0 E 18 and 1.0 E 21 atoms/cm³.

4. The method of claim 1, wherein said N⁺ doped regions are heavily doped with phosphorus (P) to a concentration of between about 1.0 E 18 and 1.0 E 21 atoms/cm³.

5. The method of claim 1, wherein said silicon epitaxy layer is deposited by chemical vapor deposition (CVD) using dichiorosilane (SiCl₂ H₂) as the reactant gas.

6. The method of claim 1, wherein said silicon epitaxy layer is deposited to a thickness of between about 1000 and 9000 Angstroms.

7. The method of claim 1, wherein said P-wells are doped with boron (B) to a concentration of between about 1.0 E 17 and 1.0 E 19 atoms/cm³.

8. The method of claim 1, wherein said field oxide isolation regions are formed by thermal oxidation of said silicon epitaxy layer by the conventional LOCal Oxidation of Silicon (LOCOS) method.

9. The method of claim 1, wherein said field oxide isolation regions are formed using a shallow trench isolation (STI) method.

10. The method of claim 1, wherein said isotropic and selective etching of said N⁺ doped regions is carried out using plasma etching in a chlorine gas.

11. The method of claim 1, where in said interelectrode layer is composed of a silicon oxide-silicon nitride-silicon oxide (ONO) having a thickness of between about 30 and 50 Angstroms.

12. The method of claim 1, wherein said doped polysilicon layer is deposited to a thickness sufficient to completely fill said holes in said silicon epitaxy layer.

13. A method of manufacturing an array of dynamic random access memory (DRAM) cells having an array of buried reservoir capacitors on and in a silicon substrate comprising the steps of:

forming a first photoresist implant mask having an array of openings on said silicon substrate;

forming N⁺ doped regions in said silicon substrate in said openings by ion implantation while said first photoresist implant mask prevents ion implantation elsewhere in said silicon substrate;

removing said first photoresist implant mask;

growing a silicon epitaxy layer on said silicon substrate;

forming an array of P-wells in said silicon epitaxy layer over said N⁺ doped regions by using a patterned second photoresist implant mask;

removing said second photoresist implant mask;

depositing a pad oxide and a silicon nitride layer and forming open areas in said silicon nitride layer in which field oxide isolation regions are required;

forming said field oxide isolation regions surrounding and electrically isolating device areas, said device areas aligned over said N⁺ doped regions;

anisotropically etching holes in said device areas through said silicon nitride layer and said P-wells in said silicon epitaxy layer to said N⁺ doped regions;

isotropically and selectively etching in said holes and thereby removing said N⁺ doped regions, and forming cavities in said silicon substrate;

removing said silicon nitride layer by etching;

depositing an interelectrode dielectric layer on surface of said cavities and on sidewalls of said holes;

depositing a doped polysilicon layer on said interelectrode dielectric layer on said surface of said cavities and filling said holes, said doped polysilicon layer in said holes forming anode electrical contacts for said buried reservoir capacitors;

chemical/mechanically polishing back said doped polysilicon layer to surface of said substrate, thereby completing said array of buried reservoir capacitors;

and further, forming said array of DRAM cells by,

growing a gate oxide on said device areas;

depositing and patterning a first polycide layer forming field effect transistor (FET) gate electrodes on said device areas extending over said buried reservoir capacitors, and concurrently forming word lines over said field oxide isolation regions;

forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;

depositing and etching back a conformal insulating layer and forming sidewall spacers on said gate electrodes;

forming source/drain contact areas adjacent to said sidewall spacers by ion implantation to form FET access transistors for said array of DRAM cells, one of said source/drain areas of each said transistor extending over one of said anode electrical contacts of said buried reservoir capacitors;

depositing and patterning a conducting layer to form a node strap over said interelectrode dielectric layer to form an electrical connection between said source/drain area and said anode electrical contact;

depositing a polysilicon/metal dielectric (PMD) layer to insulate said FET gate electrodes and said source/drain areas;

etching bit line contact holes in said polysilicon/metal dielectric layer to second of said source/drain areas of each of said FETs;

depositing and patterning a second polycide layer to form bit lines extending over and in said bit line contact holes, thereby completing said array of DRAM cells.

14. The method of claim 13, wherein said silicon substrate is a single crystal silicon conductively doped N-type with arsenic to a concentration of between about 1.0 E 15 and 1.0 E 18 atoms/cm³.

15. The method of claim 13, wherein said N⁺ doped regions are heavily doped with arsenic (As) to a concentration of between about 1.0 E 18 and 1.0 E 21 atoms/cm³.

16. The method of claim 13, wherein said N⁺ doped regions are heavily doped with phosphorus (P) to a concentration of between about 1.0 E 18 and 1.0 E 21 atoms/cm³.

17. The method of claim 13, wherein said silicon epitaxy layer is deposited by chemical vapor deposition (CVD) using dichlorosilane (SiCl₂ H₂) as the reactant gas.

18. The method of claim 13, wherein said silicon epitaxy layer is deposited to a thickness of between about 1000 and 9000 Angstroms.

19. The method of claim 13, wherein said P-wells are doped with boron (B) to a concentration of between about 1.0 E 17 and 1.0 E 19 atoms/cm³.

20. The method of claim 13, wherein said field oxide isolation regions are formed by thermal oxidation of said silicon epitaxy layer by the conventional LOCal Oxidation of Silicon (LOCOS) method.

21. The method of claim 13, wherein said field oxide isolation regions are formed using a shallow trench isolation (STI) method.

22. The method of claim 13, wherein said isotropic and selective etching of said N⁺ doped regions is carried out using plasma etching in a chlorine gas.

23. The method of claim 13, wherein said interelectrode layer is composed of a silicon oxide-silicon nitride-silicon oxide (ONO) having a thickness of between about 30 and 50 Angstroms.

24. The method of claim 13, wherein said interelectrode dielectric layer is composed of tantalum pentoxide (Ta₂ O₅).

25. The method of claim 13, wherein said doped polysilicon layer is deposited to a thickness sufficient to completely fill said holes in said silicon epitaxy layer.

26. The method of claim 13, wherein said node strap is composed of a material from the group that includes titanium silicide, cobalt silicide, and titanium nitride, and is deposited to a thickness of between about 100 and 800 Angstroms.