Direct memory access unit having a definable plurality of transfer channels

• US 5,944,800 A
• Filed: 09/12/1997
• Issued: 08/31/1999
• Est. Priority Date: 09/12/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rohm, Peter, Mattheis, Karl-Heinz
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Elamin, Abdelmoniem I
• Application Number:
  US08/928,558
• Time in Patent Office: 718 Days
• Field of Search: 395/821, 395/892, 395/725, 710/1, 710/22, 710/72, 710/23
• US Class Current: 710/23
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.

Claims

1. Direct memory access unit having a definable plurality of transfer channels comprising:

a data processing unit having a bus interface unit being coupled with a bus for transferring data, said data processing unit executing a data transfer on said bus dependent on programmable parameters; and

a parameter memory storing said parameters for each transfer channel, whereby said parameter memory provides a first memory area storing for each defined transfer channel data comprising a vector address to a second memory area comprising specific parameters for said transfer channel and a transfer instruction defining the number of parameters stored in said second memory area.

2. Unit as in claim 1, wherein said data processing unit comprises a data manipulating unit which upon said programmed parameters is able to alter said data being transferred on said bus.

3. Unit as in claim 2, wherein said manipulating unit comprises an arithmetic operator.

4. Unit as in claim 2, wherein said manipulating unit comprises a logical operator.

5. Unit as in claim 2, wherein said manipulating unit comprises a compare unit.

6. Unit as in claim 1, wherein said parameters comprise a source pointer, a destination pointer, a transfer counter, and a channel command.

7. Unit as in claim 6, wherein said parameters further comprise a data manipulate register.

8. Unit as in claim 7, wherein said parameters further comprise a second source pointer.

9. Unit as in claim 1, wherein said parameter memory is a dual port memory.

10. Direct memory access unit having a definable plurality of transfer channels comprising:

a code memory storing instructions,

a data processing unit connected to said code memory having a bus interface unit being coupled with a bus for transferring data, said data processing unit executing a data transfer on said bus by executing a program stored in said code memory, and which is dependent on programmable parameters, wherein said parameters comprise a source pointer, a destination pointer, a transfer counter, and a channel command; and

a parameter memory storing said parameters for each transfer channel, whereby said code memory provides a first memory area and a second memory area, said first memory area storing for each defined transfer channel an entry point address in said second memory area, said second memory area containing at least one program sequence.

11. Direct memory access unit as in claim 10, wherein said code memory provides a third memory area storing for each defined transfer channel a word comprising a vector address to a fourth memory area comprising specific parameters for said transfer channel.

12. Unit as in claim 11, wherein said fourth memory area is located in said code memory.

13. Unit as in claim 11, wherein said fourth memory area is located in said parameter memory.

14. Unit as in claim 10, wherein said code memory is connected to said bus.

15. Unit as in claim 10, wherein said code memory is a non volatile flash memory.

16. Unit as in claim 10, wherein said data processing unit comprises a data manipulating unit which upon said programmed parameters is able to alter said data being transferred on said bus.

17. Unit as in claim 16, wherein said manipulating unit comprises an arithmetic operator.

18. Unit as in claim 16, wherein said manipulating unit comprises a logical operator.

19. Unit as in claim 16, wherein said manipulating unit comprises a compare unit.

20. Unit as in claim 10, wherein said parameters further comprise a data manipulate register.

21. Unit as in claim 10, wherein said parameters further comprise a second source pointer.

22. Unit as in claim 10, wherein said parameter memory is a dual port memory.