FPGA input output buffer with registered tristate enable

• US 5,944,813 A
• Filed: 04/08/1997
• Issued: 08/31/1999
• Est. Priority Date: 08/03/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/840,560
• Time in Patent Office: 875 Days
• Field of Search: 395/800.36, 395/872, 326/37, 326/38, 326/41, 326/56, 326/62
• US Class Current: 712/36
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.

Claims

1. An input output buffer for an FPGA, comprising:

a pad;

a tristate buffer optionally driving said pad and having a tristate control terminal;

a first flip-flop providing an output signal through said tristate buffer to said pad; and

a second flip-flop providing a signal to said tristate control terminal for controlling impedance of said tristate buffer.

2. The input output buffer of claim 1, wherein said first and second flip-flops are addressable.

3. The input output buffer of claim 1, wherein said first and second flip-flops are separately addressable.

4. The input output buffer of claim 1, further comprising:

a third flip-flop driven by said pad and optionally providing an input signal to said FPGA.

5. The input output buffer of claim 4, wherein said first, second, and third flip-flops are addressable.

6. The input output buffer of claim 4, wherein said first, second, and third flip-flops are separately addressable.