Integrated circuit and method for decorrelating an instruction sequence of a program

• US 5,944,833 A
• Filed: 11/07/1997
• Issued: 08/31/1999
• Est. Priority Date: 03/07/1996
• Status: Expired due to Term

• Current Assignee: Gemalto SA (Thales SA)
• Original Assignee: CP8 TRANSAC
• Inventors: Ugon, Michel
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/945,845
• Time in Patent Office: 662 Days
• Field of Search: 395/551, 395/384, 395/392, 395/569, 713/400, 712/208, 712/216, 712/220, 712/228, 712/226
• US Class Current: 713/400
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/80 in storage media based on magnetic or optical technology, e.g. disks with sectors preventing unauthorised reproduction or copying of disc-type recordable media G11B20/00
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

The present invention relates to an improved integrated circuit for a microprocessor controlled by at least one program and the process for using the circuit which includes means which can decorrelate the running of at least one instruction sequence of a program from internal or external electrical signals of the integrated circuit. The internal or external electrical signals include timing, synchronization and status signals.

Claims

1. A process including a main program having interrupt sequences arranged to execute at least one operation and at least one instruction sequence in a microprocessor in synchronization with internal or external electrical signals of an integrated circuit comprising means for decorrelating an execution of the at least one instruction sequence of the program from the internal or external electrical signals of the integrated circuit so that the execution of the at least one instruction sequence is desynchronized with respect to the internal or external electrical signals, characterized in that the process comprises at least one of the following steps:

a) triggering the sequencing of one of at least one instruction or at least one operation with the aid of a random-pulse clock;

b) randomly triggering the interrupt sequences;

c) triggering the processing of a random sequence of instructions or operations during the execution of a main sequence of instructions or operations;

d) combining at least two of steps a, b and c.

2. An integrated circuit comprising a microprocessor controlled by at least one program including at least one program interrupt, the at least one program being arranged to execute at least one instruction sequence in the microprocessor in synchronization with internal or external electrical signals of the integrated circuit and means for decorrelating execution of the at least one instruction sequence of the program from the internal or external electrical signals of the integrated circuit so that the execution of the at least one instruction sequence is desynchronized with respect to the internal or external electrical signals and the program having an instruction sequence for authorization, modification, or disablement of the decorrelation means, wherein authorization includes unmasking the program interrupts.

3. An integrated circuit according to claim 2, characterized in that the decorrelation means comprises means for generating one of a timing signal, and a sequence of clock pulses which is dispatched at random times, and used to sequence one of means for randomly generating interrupts and means for triggering the execution of a secondary sequence.

4. An improved integrated circuit comprising a microprocessor having a main program arranged to execute at least one instruction sequence in the microprocessor in synchronization with internal or external electrical signals of the integrated circuit and means for decorrelating an execution of the at least one instruction sequence of the main program from the internal or external electrical signals of the integrated circuit so that the execution of the at least one instruction sequence is desynchronized with respect to the internal or external electrical signals.

5. The integrated circuit according to claim 4, characterized in that the decorrelation means comprises at least one circuit for generating a sequence of timing pulses which are dispatched at random times to the microprocessor by generation of a random number.

6. The integrated circuit according to claim 4, characterized in that the decorrelation means comprises a random interrupt generating system.

7. The integrated circuit according to claim 4, characterized in that said integrated circuit includes logic circuits and connecting busses connected such that sequencing of operations of the microprocessor factors in times required to access logic circuits of the integrated circuit, including signal propagation times in the busses and through the logic circuits.

8. The integrated circuit according to claim 4, characterized in that the decorrelation means comprises means for execution of a secondary program, the secondary program including a random choice of one of a plurality of sequences, the plurality of sequences including sequences each having a different set of instructions and a different execution time than all other ones of the plurality of sequences.

9. The integrated circuit according to claim 8, characterized in that the secondary program sequence generates a variable duration, wherein the variable duration depends on a value supplied by a random number generator.

10. The integrated circuit according to claim 8, characterized in that the secondary program sequence does not modify a general operational context of the main program, thus making it possible to return to the main program without having to re-establish the general operational context, wherein the general operational context includes at least a next instruction following a last instruction executed.

11. The integrated circuit according to claim 10, characterized in that the secondary program sequence re-establishes the general operational context of the main program before returning the control of the microprocessor to the main program.

12. The integrated circuit according to claim 4, characterized in that the main program can enable or disable the decorrelation means.

13. The integrated circuit according to claim 12, characterized in that the decorrelation means comprises at least one circuit for generating a sequence of timing pulses which are dispatched at random times to the microprocessor by generation of a random number.

14. The integrated circuit according to claim 12, characterized in that the decorrelation means comprises a random number generator for de-synchronizing execution of the at least one instruction sequence in the microprocessor.

15. The integrated circuit according to claim 12, characterized in that the decorrelation means comprises a random interrupt generating system.

16. The integrated circuit according to claim 12, characterized in that the decorrelation means comprises means for execution of a secondary program, the secondary program including a random choice of one of a plurality of sequences, the plurality of sequences including sequences each having a different set of instructions and a different execution time than all other ones of the plurality of sequences.

17. The integrated circuit according to claim 4, characterized in that the decorrelation means comprises a random number generator for de-synchronizing execution of the at least one instruction sequence in the microprocessor.

18. The integrated circuit according to claim 17, characterized in that the decorrelation means comprises a clock calibration circuit for eliminating timing pulses that are below a predetermined length.

19. The integrated circuit according to claim 17, wherein the random number generator includes counters which may or may not be looped, and which are initialized to a random value.

20. The integrated circuit according to claim 19, characterized in that the random number generator uses an algorithm of the cryptographic type or a hash function initialized to the initialization random value.

21. The integrated circuit according to claim 19, characterized in that the initialization value for the counters originates from a non-volatile memory.

22. The integrated circuit according to claim 21, characterized in that the initialization value for the counters is modified during the execution of a program.

23. The integrated circuit according to claim 4, characterized in that the electrical signals are timing, synchronization and status signals.

24. The integrated circuit according to claim 23, further includes means for phase shifting the timing, synchronization or status signals of the processor.

25. The integrated circuit according to claim 24, characterized in that the phase shifting means generates a random phase shift of the timing, synchronization or status signals of the processor.

26. The integrated circuit according to claim 25, characterized in that the phase shifting means is connected to an external clock for partially or totally de-synchronizing the operation of the processor from the external clock during the execution of a program.