Controlling flash memory program and erase pulses

• US 5,944,837 A
• Filed: 08/18/1997
• Issued: 08/31/1999
• Est. Priority Date: 10/24/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pathak, Bharat, Rozman, Rodney R., Talreja, Sanjay S., Fandrich, Mickey Lee
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/912,349
• Time in Patent Office: 743 Days
• Field of Search: 713/600, 713/502, 711/103, 365/218, 365/185.29
• US Class Current: 713/600
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.

Claims

1. An operation control apparatus comprising:

a timer circuit adapted to provide a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal;

a blocking circuit adapted to receive the done signal and to provide the done signal as output if the done signal is not blocked when received;

a control circuit adapted to receive a begin signal and a limit signal, the begin signal indicating that the operation is to be performed, the limit signal indicating whether a condition exists that would prevent the operation from being completed in a single step;

if the limit signal indicates the operation can be completed in the single step, the control circuit starting the timing circuit and controlling performance of the single step until the done signal is received;

if the limit signal indicates the operation cannot be completed in the single step, the control circuit dividing the single step into at least two sub-steps, during each sub-step, the control circuit starting the timing circuit and controlling performance of the sub-step until the done signal is received, the control circuit blocking the done signal during each sub-step until a final sub-step.

2. The apparatus of claim 1 wherein the operation to be performed is an erase operation that specifies an erase block to be erased within a flash memory.

3. The apparatus of claim 2 wherein the condition that exists that would prevent the erase block operation from being completed in a single step is insufficient erase current available to erase the entire erase block.

4. The apparatus of claim 3 wherein the single step is that of applying an erase pulse to the entire erase block to be erased.

5. The apparatus of claim 4 wherein if there is insufficient erase current available to erase the entire erase block using one erase pulse, the erase block is divided into sub-blocks and the erase pulse is supplied to a different one of the sub-blocks during each of the sub-steps.

6. The apparatus of claim 1 wherein the operation to be performed is a program operation that specifies data to be programmed within a flash memory.

7. The apparatus of claim 6 wherein a word of the data is specified.

8. The apparatus of claim 7 wherein the condition that exists that would prevent the program operation from being completed in a single step is insufficient program current available to program the entire word of data at once.

9. The apparatus of claim 8 wherein the single step is that of applying a program pulse to program the entire word of data to be programmed at once.

10. The apparatus of claim 9 wherein if there is insufficient program current available to program the entire word of data using one program pulse, the word of data to program is divided into sub-portions, a different one of the sub-portions is used to form a masked word during each of the sub-steps and the program pulse is supplied during each of the sub-steps.

11. The apparatus of claim 10 wherein the masked word to program during each of the sub-steps is formed by setting each bit of the word to program to one if the bit of the word to program does not belong to the sub-portion being programmed during the sub-step.

12. The apparatus of claim 11 wherein the program current can program at most N zeros at a time and the sub-portions are formed using no more than N bits of the word of data each sub-step.

13. The apparatus of claim 12 wherein the program current can program at most N zeros at a time and the sub-portions are formed so that at most N zeros of the word of data are programmed during each sub-step.

14. The apparatus of claim 1 wherein the begin signal is received from a state machine and the done signal is provided to the state machine if provided as output from the blocking circuit.

15. The apparatus of claim 14 wherein the state machine is a write state machine for a flash memory.

16. The apparatus of claim 14 wherein the state machine is a programmable logic array.

17. The apparatus of claim 14 wherein the state machine is a microprocessor operating under the control of a control program.

18. An operation control method comprising the steps of:

receiving an indication that an operation is to be performed;

determining whether a condition exists that would prevent the operation from being completed in a single step;

if the operation can be completed in the single step, performing the single step;

if the operation cannot be completed in the single step, dividing the single step into at least two sub-steps and performing each of the sub-steps until the operation has been performed; and

generating an indication that the operation has been performed when the operation to be performed has been completed.

19. The method of claim 18 wherein the operation to be performed is an erase operation that specifies an erase block to be erased within a flash memory.

20. The method of claim 19 wherein the condition that exists that would prevent the erase block operation from being completed in a single step is insufficient erase current available to erase the entire erase block.

21. The method of claim 20 wherein the single step is that of applying an erase pulse to the entire erase block to be erased.

22. The method of claim 21 wherein if there is insufficient erase current available to erase the entire erase block using one erase pulse, the erase block is divide into sub-blocks and the erase pulse is supplied to a different one of the sub-blocks during each of the sub-steps.

23. The method of claim 18 wherein the operation to be performed is a program operation that specifies data to be programmed within a flash memory.

24. The method of claim 23 wherein a word of the data is specified to be programmed during the program operation.

25. The method of claim 24 wherein the condition that exists that would prevent the program operation from being completed in a single step is insufficient program current available to program the entire word of data at once.

26. The method of claim 25 wherein the single step is that of applying a program pulse to program the entire word of data to be programmed at once.

27. The method of claim 26 wherein if there is insufficient program current available to program the entire word of data using one program pulse, the word of data to program is divided into sub-portions, a different one of the sub-portions is used to form a masked word during each of the sub-steps and the program pulse is supplied during each of the sub-steps.

28. The method of claim 27 wherein the masked word to program during each of the sub-steps is formed by setting each bit of the word to program to one if the bit of the word to program does not belong to the sub-portion being programmed during that sub-step.

29. The method of claim 28 wherein the program current can program at most N zeros at a time and the sub-portions are formed using no more than N bits of the word of data each sub-step.

30. The method of claim 29 wherein the program current can program at most N zeros at a time and the sub-portions are formed so that at most N zeros of the word of data are programmed during each sub-step.

31. The method of claim 18 wherein the indication that the operation to be performed is received from a state machine and the indication that the operation has been performed is provided to the state machine.

32. The method of claim 31 wherein the state machine is a write state machine for a flash memory.

33. The method of claim 31 wherein the state machine is a programmable logic array.

34. The method of claim 31 wherein the state machine is a microprocessor operating under the control of a control program.

35. Method comprising the steps of:

receiving an erase command for a portion of a memory, and, in response to the erase command;

(1) dividing an erase operation into sequential erase operations performed on two or more respective subsections of the portion of the memory if an amount of current available for erasure is below a predetermined amount; and

;

(2) performing an erase operation on the portion of the memory without dividing the portion of the memory with respect to erase operations if the amount of current available for erasure is above the predetermined amount.

36. The method of claim 35, wherein the erase command is received from a write state machine on the memory.

37. The apparatus of claim 35, wherein the portion of the memory is a block of memory.

38. A method comprising the steps of:

(1) generating an erase command for a portion of a memory array, wherein the erase command is not dependent upon an amount of current available for erasure;

(2) receiving the erase command, and, in response to the erase command;

(a) dividing an erase operation into sequential erase operations performed on two or more respective subsections of the portion of the memory array if the amount of current available for erasure is below a predetermined amount, and;

(b) performing an erase operation on the portion of the memory array without dividing the portion of the memory array with respect to erase operations if the amount of current available for erasure is above the predetermined amount.

39. A method comprising the steps of:

receiving a program command for a portion of memory, and, in response to the program command;

(1) dividing a program operation into sequential program operations performed on two or more respective subsections of the portion of memory if an amount of current available for programming is below a predetermined amount; and

,

(2) performing a program operation on the portion of memory without dividing the portion of memory with respect to program operations if the amount of current available for programming is above the predetermined amount.

40. A method comprising the steps of:

receiving a program command for a portion of memory, and, in response to the program command;

(1) dividing a program operation into sequential program operations performed by applying two or more different bit patterns to the portion of memory if an amount of current available for programming is below a predetermined amount, and,

(2) performing a program operation on the portion of memory without sequentially applying two or more different bit patterns to the portion of memory if the amount of current available for programming is above a predetermined amount.