Three-dimensional non-volatile memory

• US 5,945,705 A
• Filed: 08/01/1995
• Issued: 08/31/1999
• Est. Priority Date: 08/01/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang W., Haddad, Sameer S.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Cao, Phat X.
• Application Number:
  US08/510,118
• Time in Patent Office: 1,491 Days
• Field of Search: 257/330, 257/315, 257/316, 257/408, 257/332, 438/259, 438/242, 438/268, 438/270, 438/271, 438/257
• US Class Current: 257/315
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A strip of a semiconductor material (for example, P type silicon) is oxidized and the resulting strip of oxide is removed leaving a depression in the upper surface of the semiconductor material which has steep sidewalls. The steep sidewalls do not have significant ion impact damage because they are formed by oxidation and not by reactive ion etching of the semiconductor material. A high quality tunnel oxide can therefore be grown on the steep sidewalls. Floating gates are then formed on the tunnel oxide, corresponding word lines are formed over the floating gates, a conductive region (for example, N type silicon) is formed into the bottom of the depression, and a number of conductive regions (for example, N type silicon) corresponding with the floating gates are formed above the rim of the depression. The resulting bit transistors have channel regions which extend in a vertical dimension under floating gates along the surface of the sidewall. Because the depth and profile of the depression is determined primarily by oxidation and not by lithography, very small geometry bit transistors can be made.

Claims

1. A memory structure comprising:

a semiconductor material having an upper surface, said upper surface comprising a first substantially lateral and planar surface, a sidewall surface, and a second substantially lateral and planar surface, said first surface being laterally and vertically displaced with respect to said second surface, the semiconductor material at said sidewall surface being substantially free of ion impact damage;

a source region extending into said semiconductor material from said first surface;

a drain region extending into said semiconductor material from said second surface;

a first layer of insulator material disposed on said sidewall surface;

a floating gate disposed on said first layer of insulator material;

a second layer of insulator material disposed on said floating gate; and

a conductive layer disposed on said second layer of insulator material, said second layer of insulator material separating said floating gate and said conductive layer.

2. The memory structure of claim 1, wherein said conductive layer is a word line extending along said sidewall surface in a first dimension, said memory structure further comprising:

a bit line extending in a second dimension substantially perpendicular to said first dimension, said bit line being coupled to said drain region.

3. The memory structure of claim 2, wherein said floating gate is a layer of polysilicon.

4. The memory structure of claim 3, wherein said word line comprises polysilicon.

5. The memory structure of claim 3, wherein said second layer of insulator material comprises a first layer of oxide, a layer of nitride, and a second layer of oxide.

6. A memory structure comprising:

a semiconductor material of a first conductivity type having an upper surface, said upper surface having first and second elongated depressions which extend in a first dimension, each of said elongated depressions having opposing steep sidewalls and a bottom surface, the semiconductor material at said steep sidewalls being substantially free of ion impact damage;

a first insulator layer disposed on said sidewalls of said first and second depressions;

a first plurality of strips of a conductive layer, a respective one each of said first plurality of strips extending in said first dimension over a respective one of said sidewalls and being insulated from said sidewalls;

a second plurality of strips of a conductive layer, each of said second plurality of strips extending substantially parallel to the others of said second plurality of strips and extending in a second dimension substantially perpendicular to said first dimension, each of said second plurality of strips crossing over said first plurality of strips and crossing over said first and second depressions;

a plurality of floating gates, a respective one of said floating gates being disposed near each respective location where one of said second plurality of strips crosses one of said first plurality of strips, each floating gate being disposed between one of said first plurality of strips and the sidewall over which said strip is disposed;

a second insulator layer, each floating gate being insulated from the one of said second plurality of strips which crosses over said each floating gate;

first and second elongated conductive regions of a second conductivity type opposite said first conductivity type, said first elongated conductive region extending into said bottom surface of said first depression, said second conductive region extending into said bottom surface of said second depression; and

a plurality of third conductive regions of said second conductivity type extending into said semiconductor material between said first and second depressions, a respective one of said third conductive regions being disposed underneath and being coupled to a respective one of said second plurality of strips.

7. The memory structure of claim 6, wherein said plurality of floating gates are polysilicon gates, said first plurality of strips comprises polysilicon, said second plurality of strips are metal strips.

8. The memory structure of claim 7, wherein said first plurality of strips are word lines and wherein said second plurality of strips are bit lines.

9. The memory structure of claim 6, wherein said elongated depressions have opposing gradually sloping sidewalls in addition to said steep sidewalls.

10. The memory structure of claim 6, further comprising:

a plurality of oxide spacers, part of said oxide spacers being disposed on side-edges of said floating gates and on side-edges of said first plurality of strips.

11. The memory structure of claim 6, wherein each of said first and second elongated conductive regions comprises:

a first relatively shallow region disposed under one of said first plurality of strips disposed over a sidewall of a depression;

a second relatively shallow region disposed under another of said first plurality of strips disposed over the opposing sidewall of said depression; and

a relatively deep region disposed between said first and second relatively shallow regions and contacting said first and second relatively shallow regions.