DRAM cell with grooved transfer device

• US 5,945,707 A
• Filed: 04/07/1998
• Issued: 08/31/1999
• Est. Priority Date: 04/07/1998
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Hakey, Mark C., Bronner, Gary B., Furukawa, Toshiharu, Horak, David V., Holmes, Steven J., Mandelman, Jack A., Rabidoux, Paul A.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/056,903
• Time in Patent Office: 511 Days
• Field of Search: 257/330, 257/331
• US Class Current: 257/330
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

Claims

1. A semiconductor device comprising:

first and second regions of a first conductivity type formed in a substrate of a second conductivity type; and

a grooved gate formed in a groove located in said substrate between said first and second regions;

said grooved gate having sidewall portions and a bottom portion, and defining a channel located in said substrate along said gate sidewall and bottom portions;

sidewall sections of said channel located along said gate sidewall portion having a larger length than a bottom length of a bottom section of said channel located along said gate bottom portion so that said gate sidewall portions of said channel control said device.

2. The semiconductor device of claim 1 further comprising an isolation region formed in said substrate to isolate said semiconductor device;

said isolation region having a depth which is greater than a depth of said groove.

3. The semiconductor device of claim 1 further comprising a deep trench capacitor formed in said substrate, said deep trench capacitor having a storage electrode electrically connected to one of said first and second regions.

4. The semiconductor device of claim 1 further comprising a doped well region located between said substrate and said groove.

5. The semiconductor device of claim 1, wherein said gate sidewall portions control said semiconductor device more than said gate bottom portions.

6. The semiconductor device of claim 1, wherein one of said channel sidewall sections located along one of said gate sidewall portions has a larger length than said bottom length of said bottom channel section.

7. The semiconductor device of claim 1, wherein a length of said groove approximately equals a width of said channel.

8. The semiconductor device of claim 1, wherein a length of said channel includes a width of said groove along said gate bottom portion.

9. The semiconductor device of claim 1, wherein a length of said channel includes a depth and a width of said groove.

10. The semiconductor device of claim 1, wherein said first and second regions are separated from said groove by top lateral sections of said channel, and said grooved gate extends over said top lateral channel sections to said first and second regions.

11. The semiconductor device of claim 10, wherein said extended grooved gate extends a length of said channel to include distances of said top lateral channel sections, said channel sidewall sections and said channel bottom section.

12. The semiconductor device of claim 1, wherein said groove is a stepped groove and said grooved gate is a stepped grooved gate;

each of said gate sidewalls being separated by a lateral step into top and bottom sidewall parts.

13. The semiconductor device of claim 12, wherein an upper width of said groove between said top sidewall parts is larger than a lower width of said groove between said bottom sidewall parts.

14. The semiconductor device of claim 1, wherein said groove is centered between said first and second regions.

15. The semiconductor device of claim 1, wherein said first and second regions are self aligned to said grooved gate.