Segmented non-volatile memory array having multiple sources

• US 5,945,717 A
• Filed: 02/26/1998
• Issued: 08/31/1999
• Est. Priority Date: 03/11/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J.
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/031,972
• Time in Patent Office: 551 Days
• Field of Search: 365/218, 365/185.11, 365/185.12, 257/390, 257/401, 257/314, 257/315, 257/316, 257/920
• US Class Current: 257/390
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns. The metallic source line of one of the erase blocks extends over, but is not connected to, the adjacent erase block, with the source lines of the erase blocks preferably being connected to a common source line decoder used to control the status of a selected one of the source lines so that a selected one of the erase blocks can be erased.

Claims

1. A flash memory device comprising:

an array of memory cell floating gate transistors arranged in rows and columns;

horizontal semiconductor source lines coupled to sources of memory cell transistors located in the rows of the array;

vertical metal source lines coupled to the horizontal semiconductor source lines;

vertical metal source line straps coupled to the semiconductor source lines, the metal source lines and the metal source line straps are spaced horizontally along the semiconductor source lines to reduce a total resistance between a memory cell transistor and a vertical metal source line; and

a source line decoder circuit coupled to the vertical metal source lines for selectively coupling the vertical metal source lines of a first block of the array to a global source line, the source line decoder circuit also selectively decouples vertical metal source lines in a second block of the memory array from a voltage supply when the second block is not being accessed.

2. A flash memory device comprising:

an array of memory cells arranged in erasable blocks, each block having rows and columns, each memory cell comprising a floating gate transistor having a source, drain and gate;

a plurality of semiconductor source lines coupled to the sources of non-volatile memory cells located in a plurality of the rows of an erasable block;

a plurality of metal source lines coupled to the plurality of semiconductor source lines;

a plurality of metal source line straps coupled to the plurality of semiconductor source lines, the plurality of metal source lines and the plurality of metal source line straps are spaced along the plurality of semiconductor source lines; and

a source line decoder circuit coupled to the plurality of source lines for selectively coupling the plurality of source lines of an erasable block of the array to a global source line, the source line decoder circuit also selectively decouples the plurality of source lines in erasable blocks of the memory array from a voltage supply when those erasable blocks are not being accessed.

3. A flash memory device comprising:

a single metal interconnect layer;

an array of memory cell floating gate transistors arranged in rows and columns;

horizontal semiconductor source lines coupled to sources of memory cell transistors located in the rows of the array, the semiconductor source lines have a resistance R per unit length;

vertical metal source lines formed in the single metal interconnect layer and coupled to the horizontal semiconductor source lines;

vertical metal source line straps formed in the single metal interconnect layer and coupled to the semiconductor source lines, the metal source line straps are spaced horizontally along the semiconductor source lines to reduce a total resistance between a memory cell transistor and a vertical metal source line; and

a source line decoder circuit coupled to the vertical metal source lines for selectively coupling the vertical metal source lines of a first block of the array to a global source line, the source line decoder circuit also selectively decouples vertical metal source lines in a second block of the memory array from a voltage supply when the second block is not being accessed.