Electronic ballast with inverter control circuit

• US 5,945,788 A
• Filed: 03/30/1998
• Issued: 08/31/1999
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: OSRAM Sylvania Inc. (Ams-Osram AG)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Stephens, Dennis L., Upadhyay, Anand K., Liu, Guang, Li, Edward
• Primary Examiner(s): Philogene, Haissa
• Application Number:
  US09/050,829
• Time in Patent Office: 519 Days
• Field of Search: 315/308, 315/307, 315/224, 315/225, 315/209 R, 315/291, 315/293, 315/312, 315/314, 315/316, 315/324, 315/360, 315/362, 315/DIG. 4, 315/DIG. 7, 315/127, 315/244
• US Class Current: 315/308
• CPC Class Codes: H05B 41/2981 for protecting the circuit against abnormal operating conditions
• CPC Class Codes: Y10S 315/05 Starting and operating circuit for fluorescent lamp
• CPC Class Codes: Y10S 315/07 Starting and control circuits for gas discharge lamp using transistors

Abstract

An electronic ballast (300) for powering at least one gas discharge lamp (10) includes an inverter (400), an output circuit (700), a lamp fault detection circuit (800), and an inverter control circuit (500). Ballast (300) operates according to an inverter control method (100) that includes repeating a filament preheating step and a frequency shifting step up to a predetermined number of times in order to facilitate lamp ignition under low-temperature conditions and to verify the legitimacy of a lamp fault. Inverter control circuit (500) is well-suited for implementation as a custom integrated circuit. Ballast (300) optionally includes an overcurrent detection circuit (820'"'"') with an adjustable lamp fault detection threshold that provides decreased sensitivity during lamp starting and enhanced protection after lamp ignition.

Claims

1. An electronic ballast for powering at least one gas discharge lamp having a pair of heatable filaments, comprising:

an inverter, comprising;

first and second input terminals for receiving a source of input power, wherein the second input terminal is coupled to a circuit ground node;

an inverter output terminal;

a first inverter switch coupled between the first input terminal and the inverter output terminal;

a second inverter switch coupled between the inverter output terminal and a first node; and

an inverter control circuit coupled to the first and second inverter switches, and operable to commutate the inverter switches at a drive frequency, the inverter control circuit having a plurality of fault detection inputs and a DC supply input for receiving operating power;

a resonant output circuit coupled to the inverter output terminal, the resonant output circuit having a natural resonant frequency and a plurality of output wires coupleable to the lamp;

a lamp fault detection circuit coupled between the first node, at least one of the output wires, and the fault detection inputs of the inverter control circuit, the lamp fault detection circuit being operable to provide fault detection signals to the fault detection inputs to indicate whether or not a lamp fault condition is present; and

wherein the inverter control circuit is further operable to provide;

(a) a filament preheating mode wherein the drive frequency is maintained at a preheat frequency for a predetermined preheating period;

(b) a frequency shifting mode wherein the drive frequency is shifted from the preheat frequency to an operating frequency;

(c) a high-power operating mode wherein the drive frequency is maintained at the operating frequency in response to successful ignition and normal operation of the lamp within a predetermined ignition period, followed by continued normal operation of the lamp after ignition;

(d) a repeating mode wherein the filament preheating and frequency shifting modes are repeated up to a predetermined number of times in response to each of;

(i) failure of the lamp to ignite and operate normally within the predetermined ignition period when both lamp filaments are intact and properly connected to the output wires; and

(ii) failure of the lamp to operate normally after igniting; and

(e) a low-power protection mode wherein the drive frequency is set at the preheat frequency in response to each of;

(i) the lamp being disconnected from the ballast; and

(ii) the lamp failing to ignite and operate normally within the predetermined ignition period after the repeating mode has been carried out the predetermined number of times.

2. The electronic ballast of claim 1, wherein the low-power protection mode includes holding the drive frequency at the preheat frequency until at least such time as power to the ballast is removed or the lamp is replaced.

3. The electronic ballast of claim 1, wherein the natural resonant frequency of the resonant output circuit is closer to the operating frequency than to the preheat frequency.

4. The electronic ballast of claim 1, wherein:

the fault detection inputs of the inverter control circuit include a no-load detection (NLD) input and an overcurrent detection (OCD) input;

the lamp fault detection circuit comprises;

a no-load detection circuit coupled between at least one of the output wires and the NLD input, wherein the no-load detection circuit is operable to provide at the NLD input;

(a) a logic "1" in response to each of;

(i) both lamp filaments being intact and properly connected to the output wires; and

(ii) the lamp conducting arc current; and

(b) a logic "0" in response to each of;

(i) removal of the lamp; and

(ii) at least one lamp filament being open when the lamp is not conducting arc current; and

an overcurrent detection circuit coupled between the first node and the OCD input, wherein the overcurrent detection circuit is operable to provide at the OCD input;

(a) a logic "0" in response to the lamp operating normally when the ballast is in the high-power operating mode;

(b) a logic "1" in response to each of;

(i) failure of the lamp to ignite and operate normally within the predetermined ignition period; and

(ii) failure of the lamp to continue to operate normally after ignition.

5. The electronic ballast of claim 4, wherein the overcurrent detection circuit is further operable to provide a logic "0" at the OCD input during the filament preheating and low-power protection modes, and during at least a portion of the frequency shifting mode.

6. The electronic ballast of claim 4, wherein the inverter control circuit further comprises:

a first comparator having an inverting input coupled to the NLD input, a non-inverting input coupled to a fault reference voltage, and an output, the first comparator being operable to provide at its output;

(i) a logic "0" when the voltage at the NLD input exceeds the reference voltage; and

(ii) a logic "1" when the voltage at the NLD input is less than the reference voltage; and

a second comparator having a non-inverting input coupled to the OCD input, an inverting input coupled to the fault reference voltage, and an output, the second comparator being operable to provide at its output;

(i) a logic "1" when the voltage at the OCD input exceeds the reference voltage; and

(ii) a logic "0" when the voltage at the OCD input is less than the reference voltage.

7. The electronic ballast of claim 6, wherein the inverter control circuit further comprises a protection logic circuit having a plurality of logic inputs and a logic output, wherein the plurality of logic inputs includes a first logic input coupled to the output of the first comparator, a second logic input coupled to the output of the second comparator, a timer reset input, a power-up reset input, and a repeat disable input, wherein:

(a) the protection logic circuit is operable to provide a logic "0" at the logic output in response to a logic "0" being present at all of the logic inputs; and

(b) the protection logic circuit is operable to provide a logic "1" at the logic output in response to a logic "1" being present at at least one of;

(i) the first logic input;

(ii) the second logic input;

(iii) the power-up reset input; and

(iv) the repeat disable input.

8. The electronic ballast of claim 7, wherein the inverter control circuit further includes a preheat timing circuit, comprising:

a DC current source coupled between the DC supply input and a second node;

a timing capacitor coupled between the second node and the circuit ground node, the timing capacitor having a timing capacitor voltage; and

a discharge switch coupled in parallel with the timing capacitor and having a control lead coupled to the logic output of the protection logic circuit.

9. The electronic ballast of claim 8, wherein the inverter control circuit further includes a preheat timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to a preheat timing reference voltage, and an output, wherein the preheat timer comparator is operable to provide at its output:

(i) a logic "0" in response to the timing capacitor voltage being less than the preheat timing reference voltage; and

(ii) a logic "1" in response to the timing capacitor voltage being greater than the preheat timing reference voltage.

10. The electronic ballast of claim 9, wherein the inverter control circuit further comprises an ignition timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to an ignition timing reference voltage, and an output, wherein the ignition timer comparator is operable to provide at its output:

(i) a logic "0" in response to the timing capacitor voltage being less than the ignition timing reference voltage; and

(ii) a logic "1" in response to the timing capacitor voltage being greater than the ignition timing reference voltage.

11. The electronic ballast of claim 10, wherein the inverter control circuit further comprises a preheat reset comparator having a non-inverting input coupled to the second node, an inverting input coupled to a timer reset reference voltage, and an output coupled to the timer reset input of the protection logic circuit, the preheat reset comparator being operable to provide at its output:

(i) a logic "1" in response to the timing capacitor voltage being greater than the timer reset reference voltage; and

(ii) a logic "0" in response to the timing capacitor voltage being less than the timer reset reference voltage.

12. The electronic ballast of claim 11, wherein the inverter control circuit further includes a power-up reset circuit, comprising:

a triggering resistor coupled between the DC supply input and a third node;

a triggering capacitor coupled between the third node and the circuit ground node; and

a one-shot circuit coupled between the third node and the power-up reset input of the protection logic circuit, wherein the one-shot circuit is operable to trigger and provide a momentary logic "1" at the power-up reset input in response to the voltage at the third node reaching a predetermined trigger threshold following application of power to the ballast.

13. The electronic ballast of claim 12, wherein the inverter control circuit further comprises a counter circuit comprising:

a clock input coupled to the output of the preheat timer comparator;

a first reset input coupled to the output of the ignition timer comparator;

a second reset input coupled to the output of the first comparator;

a third reset input coupled to the power-up reset circuit; and

a counter output coupled to the repeat disable input of the protection logic circuit; and

wherein the counter circuit has a count and is operable to;

(a) initialize the count in response to a logic "1" being applied to at least one of the first, second, and third reset inputs;

(b) increment the count by one in response to the output of the preheat timing comparator changing from a logic "0" to a logic "1";

(c) provide a logic "0" at the counter output in response to the count being less than a predetermined count limit; and

(d) provide a logic "1" at the counter output in response to the count reaching the predetermined count limit.

14. The electronic ballast of claim 13, wherein the counter circuit comprises a divide-by-M counter.

15. The electronic ballast of claim 13, wherein the inverter control circuit further comprises:

a driver circuit operable to commutate the first and second inverter switches at the drive frequency and in a substantially complementary fashion, the driver circuit including a first input and a second input;

a frequency-determining resistance coupled between the first and second inputs of the driver circuit; and

a frequency-determining capacitance coupled between the second input of the driver circuit and the circuit ground node.

16. The electronic ballast of claim 15, further comprising a frequency sweep circuit coupled between the output of the preheat timer comparator and the second input of the driver circuit, wherein the frequency sweep circuit and driver circuit are operable:

(i) in response to the output of the preheat timer comparator changing from a logic "0" to a logic "1", to shift the drive frequency from the preheat frequency to the operating frequency, and then maintain the drive frequency at the operating frequency for at least as long as the output of the preheat timer comparator remains a logic "1"; and

(ii) in response to the output of the preheat timer comparator being a logic "0", to set the drive frequency to the preheat frequency, and then maintain the drive frequency at the preheat frequency for at least as long as the output of the preheat timer comparator remains a logic "0".

17. The electronic ballast of claim 16, wherein the frequency sweep circuit is operable to effectively augment the frequency-determining capacitance in response to a logic "1" being present at the output of the preheat timer comparator.

18. The electronic ballast of claim 17, wherein the frequency sweep circuit comprises:

a sweep switch having a base lead, a collector lead, and an emitter lead, the emitter lead being coupled to the circuit ground node;

a sweep timing resistor coupled between the output of the preheat timer comparator and the base lead of the sweep switch;

a sweep timing capacitor coupled between the base lead of the sweep switch and the circuit ground node; and

an augmenting capacitor coupled between the collector lead of the sweep switch and the second input of the driver circuit.

19. The electronic ballast of claim 4, wherein the inverter control circuit further comprises:

a first comparator having an inverting input coupled to the NLD input, a non-inverting input coupled to a fault reference voltage, and an output;

a second comparator having a non-inverting input coupled to the OCD input, an inverting input coupled to the fault reference voltage, and an output;

a protection logic circuit having a plurality of logic inputs and a logic output, wherein the plurality of logic inputs includes a first logic input coupled to the output of the first comparator, a second logic input coupled to the output of the second comparator, a timer reset input, a power-up reset input, and a repeat disable input, wherein the protection logic circuit is operable to provide at its logic output;

(a) a logic "0" in response to a logic "0" being present at all of the logic inputs; and

(b) a logic "1" in response to a logic "1" being present at at least one of;

(i) the first logic input;

(ii) the second logic input;

(iii) the power-up reset input; and

(iv) the repeat disable input;

a preheat timing circuit, comprising;

a DC current source coupled between the DC supply input and a second node;

a timing capacitor coupled between the second node and the circuit ground node; and

a discharge switch coupled in parallel with the timing capacitor and having a control lead coupled to the logic output of the protection logic circuit;

a preheat timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to a preheat timing reference voltage, and an output;

an ignition timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to an ignition timing reference voltage, and an output;

a preheat reset comparator having a non-inverting input coupled to the second node, an inverting input coupled to a timer reset reference voltage, and an output coupled to the timer reset input of the protection logic circuit;

a power-up reset circuit coupled between the DC supply input and the power-up reset input of the protection logic circuit, and operable to provide a momentary logic "1" at the power-up reset input following application of power to the ballast;

a counter circuit, comprising a clock input coupled to the output of the preheat timer comparator, a first reset input coupled to the output of the ignition timer comparator, a second reset input coupled to the output of the first comparator, a third reset input coupled to the power-up reset circuit, and a counter output coupled to the repeat disable input of the protection logic circuit, wherein the counter circuit has a count and is operable to;

(a) initialize the count in response to a logic "1" being applied to at least one of the first, second, and third reset inputs;

(b) increment the count by one in response to the output of the preheat timing comparator changing from a logic "0" to a logic "1";

(c) provide a logic "0" at the counter output in response to the count being less than a predetermined count limit; and

(d) provide a logic "1" at the counter output in response to the count reaching the predetermined count limit;

a driver circuit, comprising a first drive output coupled to the first inverter switch, a second drive output coupled to the second inverter switch, a reference output coupled to the inverter output terminal, a first input, and a second input;

a frequency-determining resistance coupled between the first and second inputs;

a frequency-determining capacitance coupled between the second input and the circuit ground node; and

a frequency sweep circuit coupled between the output of the preheat timer comparator and the second input of the driver circuit, and operable to effectively augment the frequency-determining capacitance of the inverter driver circuit in response to a logic "1" being present at the output of the preheat timer comparator.

20. The electronic ballast of claim 19, wherein the inverter control circuit is implemented as a single integrated circuit.

21. The electronic ballast of claim 1, wherein:

the plurality of output wires comprises first, second, third, and fourth output wires, wherein the first output wire is coupleable to the second output wire through a first filament of the lamp, and the third output wire is coupleable to the fourth output wire through a second filament of the lamp; and

the resonant output circuit further comprises;

a resonant inductor coupled between the inverter output terminal and the first output wire;

a resonant capacitor coupled between the first and fourth output wires;

a DC blocking capacitor coupled between the fourth output wire and a circuit ground node;

a filament path resistor coupled between the second and third output wires;

a first filament heating circuit coupled between the first and second output wires; and

a second filament heating circuit coupled between the third and fourth output wires.

22. The electronic ballast of claim 21, wherein:

the first filament heating circuit comprises a series combination of a first inductor and a first blocking element;

the second filament heating circuit comprises a series combination of a second inductor and a second blocking element; and

wherein the first and second inductors are magnetically coupled to the resonant inductor.

23. The electronic ballast of claim 21, wherein the no-load detection circuit comprises:

a first resistor coupled between the fourth output wire and a fourth node, wherein the fourth node is coupled to the NLD input of the inverter control circuit; and

a second resistor coupled between the fourth node and the circuit ground node.

24. The electronic ballast of claim 21, wherein the overcurrent detection circuit comprises:

a current-sensing resistor coupled between the first node and the circuit ground node;

a third resistor coupled between the first node and a fifth node, wherein the fifth node is coupled to the OCD input of the inverter control circuit; and

a first capacitor coupled between the fifth node and the circuit ground node.

25. The electronic ballast of claim 24, wherein:

the inverter control circuit further includes an ignition timing output, wherein the inverter control circuit is operable is to provide a logic "1" at the ignition timing output in response to ignition and normal operation of the lamp within the predetermined ignition period; and

the overcurrent detection circuit further comprises;

a fourth resistor coupled between the ignition timing output of the inverter control circuit and a sixth node; and

a first diode having an anode coupled to the sixth node and a cathode coupled to the fifth node.

26. An electronic ballast for powering at least two gas discharge lamps, each lamp having a pair of heatable filaments, the ballast comprising:

an inverter, comprising;

first and second input terminals for receiving a source of input power, wherein the second input terminal is coupled to a circuit ground node;

an inverter output terminal;

a first inverter switch coupled between the first input terminal and the inverter output terminal;

a second inverter switch coupled between the inverter output terminal and a first node; and

an inverter control circuit coupled to the first and second inverter switches, and operable to commutate the inverter switches at a drive frequency, the inverter control circuit having a plurality of fault detection inputs and a DC supply input for receiving operating power;

a resonant output circuit coupled to the inverter output terminals, the resonant output circuit having a natural resonant frequency and a plurality of output wires coupleable to the lamps;

a lamp fault detection circuit coupled between the first node, at least one of the output wires, and the fault detection inputs of the inverter control circuit, the lamp fault detection circuit being operable to provide fault detection signals to the fault detection inputs to indicate whether or not a lamp fault condition is present; and

wherein the inverter control circuit is further operable to provide;

(a) a filament preheating mode wherein the drive frequency is maintained at a preheat frequency for a predetermined preheating period;

(b) a frequency shifting mode wherein the drive frequency is shifted from the preheat frequency to an operating frequency;

(c) a high-power operating mode wherein the drive frequency is maintained at the operating frequency in response to successful ignition and normal operation of all of the lamps within a predetermined ignition period, followed by continued normal operation of all of the lamps after ignition;

(d) a repeating mode wherein the filament preheating and frequency shifting modes are repeated up to a predetermined number of times in response to each of;

(i) failure of at least one of the lamps to ignite and operate normally within the predetermined ignition period when all lamp filaments are intact and properly connected to the output wires; and

(ii) failure of at least one of the lamps to operate normally after igniting; and

(e) a low-power protection mode wherein the drive frequency is set to the preheat frequency in response to each of;

(i) at least one of the lamps being disconnected from the ballast; and

(ii) at least one of the lamps failing to ignite and operate normally within the predetermined ignition period after the repeating mode has been carried out the predetermined number of times.

27. The electronic ballast of claim 26, wherein:

the fault detection inputs of the inverter control circuit include a no-load detection (NLD) input and an overcurrent detection (OCD) input;

the lamp fault detection circuit comprises;

a no-load detection circuit coupled between at least one of the output wires and the NLD input, wherein the no-load detection circuit is operable to provide at the NLD input;

(a) a logic "1" in response to each of;

(i) all lamp filaments being intact and properly connected to the output wires; and

(ii) all of the lamps conducting arc current; and

(b) a logic "0" in response to each of;

(i) removal of at least one lamp; and

(ii) at least one lamp filament being open when each of the lamps is not conducting arc current; and

an overcurrent detection circuit coupled between the first node and the OCD input, wherein the overcurrent detection circuit is operable to provide at the OCD input;

(a) a logic "0" in response to all of the lamps operating normally when the ballast is in the high-power operating mode;

(b) a logic "1" in response to each of;

(i) failure of at least one of the lamps to ignite and operate normally within the predetermined ignition period; and

(ii) failure of at least one of the lamps to continue to operate normally after ignition.

28. The electronic ballast of claim 27, wherein the overcurrent detection circuit is further operable to provide a logic "0" at the OCD input during the filament preheating and low-power protection modes, and during at least a portion of the frequency shifting mode.

29. The electronic ballast of claim 27, wherein the inverter control circuit further comprises:

a first comparator having an inverting input coupled to the NLD input, a non-inverting input coupled to a fault reference voltage, and an output;

a second comparator having a non-inverting input coupled to the OCD input, an inverting input coupled to the fault reference voltage, and an output;

a protection logic circuit having a plurality of logic inputs and a logic output, wherein the plurality of logic inputs includes a first logic input coupled to the output of the first comparator, a second logic input coupled to the output of the second comparator, a timer reset input, a power-up reset input, and a repeat disable input, wherein the protection logic circuit is operable to provide at its logic output;

(a) a logic "0" in response to a logic "0" being present at all of the logic inputs; and

(b) a logic "1" in response to a logic "1" being present at at least one of;

(i) the first logic input;

(ii) the second logic input;

(iii) the power-up reset input; and

(iv) the repeat disable input;

a preheat timing circuit, comprising;

a DC current source coupled between the DC supply input and a second node;

a timing capacitor coupled between the second node and the circuit ground node; and

a discharge switch coupled in parallel with the timing capacitor and having a control lead coupled to the logic output of the protection logic circuit;

a preheat timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to a preheat timing reference voltage, and an output;

an ignition timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to an ignition timing reference voltage, and an output;

a preheat reset comparator having a non-inverting input coupled to the second node, an inverting input coupled to a timer reset reference voltage, and an output coupled to the timer reset input of the protection logic circuit;

a power-up reset circuit coupled between the DC supply input and the power-up reset input of the protection logic circuit, and operable to provide a momentary logic "1" at the power-up reset input following application of power to the ballast; and

a counter circuit, comprising a clock input coupled to the output of the preheat timer comparator, a first reset input coupled to the output of the ignition timer comparator, a second reset input coupled to the output of the first comparator, a third reset input coupled to the power-up reset circuit, and a counter output coupled to the repeat disable input of the protection logic circuit, wherein the counter circuit has a count and is operable to;

(a) initialize the count in response to a logic "1" being applied to at least one of the first, second, and third reset inputs;

(b) increment the count by one in response to the output of the preheat timing comparator changing from a logic "0" to a logic "1";

(c) provide a logic "0" at the counter output in response to the count being less than a predetermined count limit; and

(d) provide a logic "1" at the counter output in response to the count reaching the predetermined count limit.

30. The electronic ballast of claim 29, wherein the inverter control circuit further comprises:

a driver circuit, comprising a first drive output coupled to the first inverter switch, a second drive output coupled to the second inverter switch, a reference output coupled to the inverter output terminal, a first input, and a second input;

a frequency-determining resistance coupled between the first and second inputs;

a frequency-determining capacitance coupled between the second input and the circuit ground node; and

a frequency sweep circuit coupled between the output of the preheat timer comparator and the second input of the driver circuit, and operable to effectively augment the frequency-determining capacitance of the inverter driver circuit in response to a logic "1" being present at the output of the preheat timer comparator.

31. An electronic ballast for powering at least two gas discharge lamps, comprising:

an inverter, comprising;

first and second input terminals adapted to receive a source of input power, wherein the second input terminal is coupled to a circuit ground node;

an inverter output terminal;

a first inverter switch coupled between the first input terminal and the inverter output terminal;

a second inverter switch coupled between the inverter output terminal and a first node; and

an inverter control circuit comprising a first drive output coupled to the first inverter switch, a second drive output coupled to the second inverter switch, a reference output coupled to the inverter output terminal, a DC supply input, a no-load detect (NLD) input, and an overcurrent detect (OCD) input;

an output circuit, comprising;

a set of output wires comprising first, second, third, fourth, fifth, and sixth output wires adapted to being coupled to at least a first and a second gas discharge lamp, wherein the first output wire is coupleable to the second output wire through a first filament of the first lamp, the third output wire is coupleable to the fourth output wire through a second filament of the first lamp, the second filament of the first lamp is coupleable in parallel with a first filament of the second lamp, and the fifth output wire is coupleable to the sixth output wire through a second filament of the second lamp;

a resonant inductor coupled between the inverter output terminal and the first output wire;

a resonant capacitor coupled between the first and sixth output wires;

a DC blocking capacitor coupled between the sixth output wire and the circuit ground node;

a first filament path resistor coupled between the second and third output wires;

a second filament path resistor coupled between the fourth and fifth output wires;

a first filament heating circuit coupled between the first and second output wires;

a second filament heating circuit coupled between the third and fourth output wires; and

a third filament heating circuit coupled between the fifth and sixth output wires;

a no-load detection circuit coupled between the sixth output wire and the NLD input of the inverter control circuit;

an overcurrent detection circuit coupled between the first node and the OCD input of the inverter control circuit; and

wherein the inverter control circuit further comprises;

a first comparator having an inverting input coupled to the NLD input, a non-inverting input coupled to a fault reference voltage, and an output;

a second comparator having a non-inverting input coupled to the OCD input, an inverting input coupled to the fault reference voltage, and an output;

a protection logic circuit having a plurality of logic inputs and a logic output, wherein the plurality of logic inputs includes a first logic input coupled to the output of the first comparator, a second logic input coupled to the output of the second comparator, a timer reset input, a power-up reset input, and a repeat disable input;

wherein the protection logic circuit is operable to provide at its logic output;

(a) a logic "0" in response to a logic "0" being present at all of the logic inputs; and

(b) a logic "1" in response to a logic "1" being present at at least one of;

(i) the first logic input;

(ii) the second logic input;

(iii) the power-up reset input; and

(iv) the repeat disable input;

a preheat timing circuit, comprising;

a DC current source coupled between the DC supply input and a second node;

a timing capacitor coupled between the second node and the circuit ground node, and having a timing capacitor voltage; and

a discharge switch coupled in parallel with the timing capacitor and having a control lead coupled to the logic output of the protection logic circuit;

a preheat timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to a preheat timing reference voltage, and an output;

an ignition timer comparator having a non-inverting input coupled to the second node, an inverting input coupled to an ignition timing reference voltage, and an output;

a preheat reset comparator having a non-inverting input coupled to the second node, an inverting input coupled to a timer reset reference voltage, and an output coupled to the timer reset input of the protection logic circuit;

a power-up reset circuit, comprising;

a triggering resistor coupled between the DC supply input and a third node;

a triggering capacitor coupled between the third node and the circuit ground node; and

a one-shot circuit coupled between the third node and the power-up reset input of the protection logic circuit, and operable to provide a momentary voltage pulse at the power-up reset input in response to the voltage at the third node reaching a predetermined trigger threshold following application of power to the ballast;

a counter circuit, comprising;

a clock input coupled to the output of the preheat timer comparator;

a first reset input coupled to the output of the ignition timer comparator;

a second reset input coupled to the output of the First comparator;

a third reset input coupled to the pulse output of the power-up reset circuit; and

a counter output coupled to the repeat disable input of the protection logic circuit;

a driver circuit coupled to the first and second drive outputs and the reference output of the inverter control circuit, and operable to provide complementary switching of the first and second inverter switches at the drive frequency, the driver circuit including a first input and a second input;

a frequency-determining resistance coupled between the first and second inputs of the driver circuit;

a frequency-determining capacitance coupled between the second input of the driver circuit and the circuit ground node; and

a frequency sweep circuit coupled between the output of the preheat timer comparator and the second input of the driver circuit, and operable to effectively augment the frequency-determining capacitance of the inverter driver circuit in response to a logic "1" being present at the output of the preheat timer comparator.