Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
First Claim
1. A semiconductor wafer package comprising:
- a retainer board for retaining a semiconductor wafer comprising a plurality of integrated circuit terminals, said plurality of integrated circuit terminals being operable for testing a plurality of semiconductor chips disposed on said semiconductor wafer;
a wiring board provided so as to face said retainer board and comprising a plurality of probe terminals and a wire which are electrically connected to each other, said plurality of probe terminals facing, and being electrically connectable to, said plurality of integrated circuit terminals of said retainer board, respectively;
a sealing member for forming a hermetic space together with said retainer board and said wiring board, said sealing member comprising an elastic material and being provided in the periphery of said formed hermetic space; and
depressurizing means for depressurizing said hermetic space to move said retainer board and said wiring board close to each other, thereby establishing an electrical connection between said plurality of integrated circuit terminals of said semiconductor wafer retained by said retainer board and said probe terminals of said wiring board, respectively.
0 Assignments
0 Petitions
Accused Products
Abstract
A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
-
Citations
7 Claims
-
1. A semiconductor wafer package comprising:
-
a retainer board for retaining a semiconductor wafer comprising a plurality of integrated circuit terminals, said plurality of integrated circuit terminals being operable for testing a plurality of semiconductor chips disposed on said semiconductor wafer; a wiring board provided so as to face said retainer board and comprising a plurality of probe terminals and a wire which are electrically connected to each other, said plurality of probe terminals facing, and being electrically connectable to, said plurality of integrated circuit terminals of said retainer board, respectively; a sealing member for forming a hermetic space together with said retainer board and said wiring board, said sealing member comprising an elastic material and being provided in the periphery of said formed hermetic space; and depressurizing means for depressurizing said hermetic space to move said retainer board and said wiring board close to each other, thereby establishing an electrical connection between said plurality of integrated circuit terminals of said semiconductor wafer retained by said retainer board and said probe terminals of said wiring board, respectively. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A method for testing a plurality of semiconductor chips disposed on a semiconductor wafer comprising the steps of:
-
placing said semiconductor wafer comprising a plurality of integrated circuit terminals for testing said plurality of semiconductor chips so as to be retained by a retainer board; disposing a wiring board comprising a plurality of probe terminals and a wire which are electrically connected to each other and said retainer board retaining said semiconductor wafer, such that said plurality of probe terminals face said integrated circuit terminals, respectively, and further disposing a sealing member such that a hermetic space is formed by said retainer board, said wiring board and said sealing member are provided in the periphery of said hermetic space; depressurizing said hermetic space, to bring said probe terminals of said wiring board and said integrated circuit terminals of said semiconductor wafer into contact with each other; setting said wiring board, said retainer board and said sealing member while maintaining said hermetic space at a depressurized state, into a burn-in rack for testing; and
testing said plurality of semiconductor chips by inputting a power-source voltage or a signal for testing to said integrated circuit terminals of said semiconductor wafer via said wire and said probe terminals of said wiring board. - View Dependent Claims (7)
-
Specification