Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method

• US 5,945,834 A
• Filed: 02/29/1996
• Issued: 08/31/1999
• Est. Priority Date: 12/16/1993
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Uraoka, Yukiharu, Fujiwara, Atsushi, Hashimoto, Shin, Yamada, Toshio, Nakata, Yoshirou, Miyanaga, Isao, Okuda, Yasushi, Hatada, Kenzou
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US08/609,150
• Time in Patent Office: 1,279 Days
• Field of Search: 324/754, 324/757, 324/758, 324/761, 324/765
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2867 Handlers or transport devices, e.g. loaders, carriers, trays
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Claims

1. A semiconductor wafer package comprising:

a retainer board for retaining a semiconductor wafer comprising a plurality of integrated circuit terminals, said plurality of integrated circuit terminals being operable for testing a plurality of semiconductor chips disposed on said semiconductor wafer;

a wiring board provided so as to face said retainer board and comprising a plurality of probe terminals and a wire which are electrically connected to each other, said plurality of probe terminals facing, and being electrically connectable to, said plurality of integrated circuit terminals of said retainer board, respectively;

a sealing member for forming a hermetic space together with said retainer board and said wiring board, said sealing member comprising an elastic material and being provided in the periphery of said formed hermetic space; and

depressurizing means for depressurizing said hermetic space to move said retainer board and said wiring board close to each other, thereby establishing an electrical connection between said plurality of integrated circuit terminals of said semiconductor wafer retained by said retainer board and said probe terminals of said wiring board, respectively.

2. The semiconductor wafer package according to claim 1, wherein said sealing member elastically shrinks due to a pressure difference between said hermetic space and the air outside said hermetic space when said hermetic space is depressurized by said depressurizing means, to move said retainer board and said wiring board close to each other, thereby establishing an electrical connection between said integrated circuit terminals of said retainer board and said probe terminals of said wiring board.

3. The semiconductor wafer package according to claim 1, wherein said wiring board comprises a probe sheet provided so as to face said retainer board;

and an insulating board provided along a surface of said probe sheet, which surface is farther from said retainer board, wherein said plurality of probe terminals are provided on said probe sheet.

4. The semiconductor wafer package according to claim 1, wherein said wiring board comprises an external terminal which is electrically connected with said wire and receives a power-source voltage or a signal for testing from an outside source.

5. The semiconductor wafer package according to claim 1, wherein said depressurizing means comprises a suction hole joining to said hermetic space, and a valve for opening or shutting said suction hole, wherein said hermetic space is depressurized through said suction hole.

6. A method for testing a plurality of semiconductor chips disposed on a semiconductor wafer comprising the steps of:

placing said semiconductor wafer comprising a plurality of integrated circuit terminals for testing said plurality of semiconductor chips so as to be retained by a retainer board;

disposing a wiring board comprising a plurality of probe terminals and a wire which are electrically connected to each other and said retainer board retaining said semiconductor wafer, such that said plurality of probe terminals face said integrated circuit terminals, respectively, and further disposing a sealing member such that a hermetic space is formed by said retainer board, said wiring board and said sealing member are provided in the periphery of said hermetic space;

depressurizing said hermetic space, to bring said probe terminals of said wiring board and said integrated circuit terminals of said semiconductor wafer into contact with each other;

setting said wiring board, said retainer board and said sealing member while maintaining said hermetic space at a depressurized state, into a burn-in rack for testing; and

testing said plurality of semiconductor chips by inputting a power-source voltage or a signal for testing to said integrated circuit terminals of said semiconductor wafer via said wire and said probe terminals of said wiring board.

7. The method for testing a semiconductor chip according to claim 6 further comprising a step of redepressurizing said hermetic space formed by said wiring board, said retainer board and said sealing member when said wiring board, said retainer board and said sealing member are set in said burn-in rack for testing.