Distributed amplifier logic designs

• US 5,945,847 A
• Filed: 05/20/1997
• Issued: 08/31/1999
• Est. Priority Date: 05/20/1997
• Status: Expired due to Term

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Ransijn, Johannes Gerardus
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/858,968
• Time in Patent Office: 833 Days
• Field of Search: 326/9, 326/10, 326/17, 326/52-55, 326/83, 326/86, 326/112, 326/115, 326/119
• US Class Current: 326/115
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

A high speed logic module is formed to include a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines. A pair of logic devices are included in the module, with the gate terminals of the devices coupled to separate ones of the input inductive transmission lines. The output terminals of the logic devices are coupled to separate ones of the pair of output inductive transmission lines. The effects of the intrinsic gate-to-drain capacitance C_gd inherent in each logic device is compensated for by including a pair of cross-coupled neutralizing capacitors between the drain and gate terminals of the logic devices. Various logic circuits, such as oscillators, latches, delay lines, etc. can be formed using the differential, neutralized structure of the invention.

Claims

1. A high speed logic module comprising

a pair of logic devices, each device including a gate terminal, a drain terminal and a source terminal, the source terminals being coupled to receive a predetermined signal;

a differential input comprising a pair of transmission lines, each input transmission line coupled to a separate one of the gate terminals of said pair of logic devices;

a differential output comprising a pair of transmission lines, each output transmission line coupled to a separate one of the drain terminals of said pair of logic devices; and

a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between said drain terminal of a first logic device of said pair of logic devices and said gate terminal of a second logic device of said pair of logic devices, and a second neutralizing reactive element coupled between said drain terminal of said second logic device and said gate terminal of said first logic device.

2. A logic module as defined in claim 1 wherein the reactive elements comprise capacitive elements.

3. A logic module as defined in claim 2 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

4. A logic module as defined in claim 1 wherein the input and output transmission lines comprise inductive transmission lines.

5. A logic module as defined in claim 1 wherein the reactive elements comprise additional logic devices.

6. A multi-stage logic device comprising

a differential input comprising a pair of transmission lines;

a differential output comprising a pair of transmission lines; and

a plurality of logic modules coupled between the differential input and the differential output, each logic module comprising

a pair of logic devices, each device including a gate terminal, a drain terminal, and a source terminal, the source terminals being coupled to receive predetermined signals, each gate terminal coupled to a separate one of the pair of input transmission lines, and each drain terminals coupled to a separate one of the pair of output transmission lines; and

a pair of neutralizing reactive elements, a first reactive element coupled between said drain terminal of a first logic device of said pair of logic devices and said gate terminals of a second logic device of said pair of logic devices, and a second neutralizing reactive coupled between said drain terminal of said second logic device and said gate terminal of said first logic device.

7. A multi-stage logic device as defined in claim 6 wherein each reactive element comprises a capacitor.

8. A multi-stage logic device as defined in claim 7 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

9. A multi-stage logic device as defined in claim 6 wherein the reactive elements comprise logic devices.

10. A multi-stage logic device as defined in claim 6 wherein the input and output transmission lines are inductive transmission lines.

11. A distributed exclusive-OR logic circuit comprising a plurality of differential exclusive-OR logic modules, said exclusive-OR logic circuit including

a first differential input comprising a first pair of input transmission lines;

a second differential input comprising a second pair of input transmission lines;

a differential output comprising a pair of output transmission lines; and

a plurality of exclusive-OR logic modules, each exclusive -OR logic module comprising

a first pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines;

a second pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines, said second pair of logic devices disposed in a cross-coupled relationship with said first pair of logic devices in a manner whereby said second pair of logic devices provides neutralization to the intrinsic capacitance associated with said first pair of logic devices;

a third pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said second pair of input transmission lines and said pair of output transmission lines; and

a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between the drain terminal of a first logic device and gate terminals of a second logic device of said third pair of logic devices and a second neutralizing reactive element coupled between the drain terminal of said second device and the gate terminal of said first device of said third pair of logic devices.

12. A distributed exclusive-OR logic circuit as defined in claim 11 wherein the neutralizing reactive elements comprise capacitors.

13. A distributed exclusive-OR logic circuit as defined in claim 12 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

14. A distributed exclusive-OR logic circuit as defined in claim 11 wherein the neutralizing reactive elements comprise logic devices.

15. A distributed exclusive-OR logic circuit as defined in claim 11 wherein each input transmission line and output transmission line comprises an inductive transmission line.

16. A distributed latch circuit comprising

a differential signal input comprising a pair of signal input transmission lines;

a differential clock input comprising a pair of clock input transmission lines;

a differential output comprising a pair of output transmission lines; and

a plurality of latch logic circuit modules, each latch logic circuit module comprising

a first pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said first pair of logic devices coupled to separate ones of said pair of signal input transmission lines and the drain terminals of said first pair of logic devices coupled to separate ones of said pair of output transmission lines;

a first pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said first pair of logic devices;

a second pair of logic devices, each including a gate terminal, a drain terminal, and a source terminal, the gate terminals of said second pair of logic devices being coupled to separate ones of said pair of output transmission lines and the drain terminals of said second pair of logic devices coupled, in an opposing arrangement, to said pair of output transmission lines such that the gate and drain terminals of each device are coupled to different output transmission lines;

a second pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said second pair of logic devices;

a third pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said third pair of logic devices being coupled to separate ones of said pair of clock input transmission lines, the source terminals being coupled together and applied to a power supply, the drain terminal of a first device of said third pair of logic devices being coupled to both source terminals of said first pair of logic devices and the drain terminal of a second device of said third pair of logic devices being coupled to both source terminals of said second pair of logic devices; and

a third pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said third pair of logic devices.

17. A distributed latch circuit as defined in claim 16 wherein each reactive elements comprises a capacitor.

18. A distributed latch circuit as defined in claim 17 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

19. A distributed latched circuit as defined in claim 16 wherein

the pair of signal input transmission lines comprise inductive transmission lines, the pair of clock input transmission lines comprise inductive transmission lines and the pair of output transmission lines comprise inductive transmission lines.

20. An integrated circuit including a high speed logic module comprising

a pair of logic devices, each device including a gate terminal, a drain terminal and a source terminal, the source terminals being coupled to receive a predetermined signal;

a differential input comprising a pair of transmission lines, each input transmission line coupled to a separate one of the gate terminals of said pair of logic devices;

a differential output comprising a pair of transmission lines, each output transmission line coupled to a separate one of the drain terminals of said pair of logic devices; and

a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between said drain terminal of a first logic device of said pair of logic devices and said gate terminal of a second logic device of said pair of logic devices, and a second neutralizing reactive element coupled between said drain terminal of said second logic device and said gate terminal of said first logic device.

21. An integrated circuit as defined in claim 20 wherein the reactive elements comprise capacitive elements.

22. An integrated circuit as defined in claim 21 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

23. An integrated circuit as defined in claim 20 wherein the input and output transmission lines comprise inductive transmission lines.

24. An integrated circuit as defined in claim 20 wherein each reactive element comprises an additional logic device.

25. An integrated circuit including a multi-stage logic device comprising

a differential input comprising a pair of transmission lines;

a differential output comprising a pair of transmission lines; and

a plurality of logic modules coupled between the differential input and the differential output, each logic module comprising

a pair of logic devices, each device including a gate terminal, a drain terminal, and a source terminal, the source terminals being coupled to receive predetermined signals, each gate terminal coupled to a separate one of the pair of input transmission lines, and each drain terminals coupled to a separate one of the pair of output transmission lines; and

a pair of neutralizing reactive elements, a first reactive element coupled between said drain terminal of a first logic device of said pair of logic devices and said gate terminals of a second logic device of said pair of logic devices, and a second neutralizing reactive coupled between said drain terminal of said second logic device and said gate terminal of said first logic device.

26. An integrated circuit as defined in claim 25 wherein each reactive element comprises a capacitor.

27. An integrated circuit as defined in claim 26 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

28. An integrated circuit as defined in claim 25 wherein the reactive elements comprise logic devices.

29. An integrated circuit as defined in claim 25 wherein the input and output transmission lines are inductive transmission lines.

30. An integrated circuit including a distributed exclusive-OR logic circuit comprising a plurality of differential exclusive-OR logic modules, said exclusive-OR logic circuit including

a first differential input comprising a first pair of input transmission lines;

a second differential input comprising a second pair of input transmission lines;

a differential output comprising a pair of output transmission lines; and

a plurality of exclusive-OR logic modules, each exclusive-OR logic module comprising

a first pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines;

a second pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines, said second pair of logic devices disposed in a cross-coupled relationship with said first pair of logic devices in a manner whereby said second pair of logic devices provides neutralization to the intrinsic capacitance associated with said first pair of logic devices;

a third pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said second pair of input transmission lines and said pair of output transmission lines; and

a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between the drain terminal of a first logic device and gate terminals of a second logic device of said third pair of logic devices and a second neutralizing reactive element coupled between the drain terminal of said second device and the gate terminal of said first device of said third pair of logic devices.

31. An integrated circuit as defined in claim 30 wherein the neutralizing reactive elements comprise capacitors.

32. An integrated circuit as defined in claim 31 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

33. An integrated circuit as defined in claim 30 wherein each neutralizing reactive element comprises a logic device.

34. An integrated circuit defined in claim 30 wherein each input transmission line and output transmission line comprises an inductive transmission line.

35. An integrated circuit comprise a distributed latch circuit comprising

a differential signal input comprising a pair of signal input transmission lines;

a differential clock input comprising a pair of clock input transmission lines;

a differential output comprising a pair of output transmission lines; and

a plurality of latch logic circuit modules, each latch logic circuit module comprising

a first pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said first pair of logic devices coupled to separate ones of said pair of signal input transmission lines and the drain terminals of said first pair of logic devices coupled to separate ones of said pair of output transmission lines;

a first pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said first pair of logic devices;

a second pair of logic devices, each including a gate terminal, a drain terminal, and a source terminal, the gate terminals of said second pair of logic devices being coupled to separate ones of said pair of output transmission lines and the drain terminals of said second pair of logic devices coupled, in an opposing arrangement, to said pair of output transmission lines such that the gate and drain terminals of each device are coupled to different output transmission lines;

a second pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said second pair of logic devices;

a third pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said third pair of logic devices being coupled to separate ones of said pair of clock input transmission lines, the source terminals being coupled together and applied to a power supply, the drain terminal of a first device of said third pair of logic devices being coupled to both source terminals of said first pair of logic devices and the drain terminal of a second device of said third pair of logic devices being coupled to both source terminals of said second pair of logic devices; and

a third pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said third pair of logic devices.

36. An integrated circuit as defined in claim 35 wherein each reactive element comprises a capacitor.

37. An integrated circuit as defined in claim 36 wherein each neutralizing capacitor is formed to comprise a value essentially equal to an intrinsic capacitance existing between the gate and the drain of each logic device.

38. An integrated circuit as defined in claim 35 wherein the pair of input signal transmission lines comprise inductive transmission lines, the pair of clock input transmission lines comprise inductive transmission lines, and the pair of output transmission lines comprise inductive transmission lines.