CMOS comparator output circuit with high gain and hysteresis

• US 5,945,852 A
• Filed: 03/31/1998
• Issued: 08/31/1999
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kosiec, Jeannie Han
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/052,467
• Time in Patent Office: 518 Days
• Field of Search: 323/315, 327/77, 327/68, 327/72, 327/73, 327/74, 327/205, 327/206
• US Class Current: 327/68
• CPC Class Codes: H03K 3/2897 with an input circuit of differential configuration

Abstract

A comparator circuit (100) produces a binary output voltage at an output (109) in response to a time varying input signal received at an input (108). The comparator circuit includes an output circuit (106) having a first current mirror (202), a second current mirror (204), a bias circuit (206) and a helping current source (208). Bias currents are applied in response to the state of the output voltage at the output to increase the gain and the hysteresis of the output circuit.

Claims

1. A circuit which produces a binary output voltage at an output in response to a time varying input signal, the circuit comprising:

a first current mirror having a transistor that is series coupled with the output and produces a first current at the output in response to the input signal;

a second current mirror having a transistor that is series coupled with the output and produces a second current at the output in response to a bias current, the first and the second currents producing the binary output voltage having a state determined by relative magnitudes of the first current and the second current; and

a bias circuit including a bias current source, a switchable current source, and a switch coupled between the switchable current source and the second current mirror for switching the switchable current source so as to provide the bias current at one of a first value and a second value in response to the state of the binary output voltage.

2. The circuit of claim 1 wherein the switch comprises a field effect transistor having a gate electrically coupled to the output.

3. The circuit of claim 1 further comprising:

a helping current source which generates a helping current; and

a switch for combining the helping current and the input signal at the first current mirror in response to the state of the binary output voltage,

the first current increasing in response to the helping current.

4. The circuit of claim 3 wherein the switch comprises a field effect transistor having a gate electrically coupled to the output, a source coupled to the helping current source and a drain coupled to an input which receives an input current as the input signal, the field effect transistor providing the helping current to the input when the binary output voltage has a predetermined level.

5. The circuit of claim 3 wherein helping current source is mirror-connected with the second current mirror.

6. A circuit which produces a binary output voltage in response to an input current, the circuit comprising:

a first current mirror configured to receive the input current and produce a first polarity current;

a second current mirror configured to receive a bias current and produce a second polarity current, the first current mirror and the second current mirror each having a transistor series coupled with an output of the circuit to produce the binary output voltage; and

a bias circuit coupled to the second current mirror and producing the bias current at one of a first magnitude and a second magnitude responsive to state of the binary output voltage,

the bias circuit including a bias current source which produces a first portion of the bias current, a switchable current source which produces a second portion of the bias current, and a switch to switch in the switchable current source when the binary output voltage has a predetermined level so as to combine the first and second portions of the bias current.

7. The circuit of claim 6 further comprising:

a comparing stage which compares a time varying input voltage and a reference voltage and produces an intermediate voltage in response thereto; and

a converter coupled to the first current mirror which produces the input current in response to the intermediate voltage.

8. A comparator comprising:

an input stage which compares a time varying input voltage and a reference voltage and produces an intermediate voltage in response to the comparison;

a converter coupled to the input stage which produces an input current in response to the intermediate voltage;

an input circuit coupled to the converter and configured to receive the input current;

a comparing circuit coupled to the input circuit, the comparing circuit establishes an output voltage at a first value when the input current exceeds a first predetermined threshold of a bias current and at a second value when the input current exceeds a second predetermined threshold of the bias current; and

a bias circuit coupled to the comparing circuit, the bias circuit varies the bias current in response to the output voltage to establish hysteresis in the comparator.

9. The comparator of claim 8 wherein the comparing circuit comprises series coupled transistors each conducting an internal current, the output voltage produced at a node common to the series coupled transistors in response to magnitude of the internal current.

10. The comparator of claim 9 wherein the bias circuit comprises:

a first current source coupled to the comparing circuit and providing a first bias current; and

a switchable current source coupled to the comparing circuit and providing a switchable current,

the comparing circuit combining the first bias current and the switchable current for comparison with the input current.

11. The comparator of claim 10 wherein the comparing circuit comprises:

a first current mirror which produces the internal current in response to the input current; and

a second current mirror which produces the internal current in response to combination of the first bias current and the switchable current.

12. The comparator of claim 10 wherein the switchable current source switches in response to the output voltage.

13. The comparator of claim 8 further comprising:

a helping current source which generates a helping current; and

a switch for combining the helping current and the input current in response to state of the output voltage.