Clocked flip flop circuit with built-in clock controller and frequency divider using the same

• US 5,945,858 A
• Filed: 03/31/1998
• Issued: 08/31/1999
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Sato, Masaharu
• Primary Examiner(s): Lam, Tuan T.
• Application Number:
  US09/050,350
• Time in Patent Office: 518 Days
• Field of Search: 327/202, 327/203, 327/208-212, 327/215, 327/218, 327/115, 327/117, 327/118, 377/47, 377/48
• US Class Current: 327/202
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A clocked master slave flip flop circuit includes a current mirror circuit with a pair of field effect transistors serving as a constant current source, and the field effect transistors are gated by a clock signal and a complementary clock signal; and the clocked master slave flip flop circuit further includes a built-in logic circuits achieving logic functions inverse to each other, and one the built-in logic circuits and the other field effect transistor are connected in series of one of the field effect transistors and in parallel to the other field effect transistor; the logic circuits are responsive to a clock control signal so as to enable the constant current source, and causes the clocked master slave flip flop circuit to change or maintain a data bit stored therein.

Claims

1. A flip flop circuit comprising:

a data storage circuit comprising;

a differential amplification stage connected to a first source of power voltage and responsive to an input data signal for storing said input data signal in the form of a potential difference and

a constant current source connected to said differential amplification stage and responsive to a clock signal so as to enable said differential amplification stage; and

a clock controller connected to said constant current source of said data storage circuit for controlling said constant current source in accordance with a clock data signal wherein said differential amplification stage comprises;

a first resistor connected to said first source of power voltage,

a second resistor connected to said first source of power voltage in parallel to said first resistor,

a first transistor and a second transistor responsive to said input data signal and a complimentary input data signal for producing a first current path between one of said first and second resistors and a first node and producing said potential difference between a second node connected to said first resistor and a third node connected to said second resistor and,

a third transistor and a fourth transistor connected in parallel to said first transistor and said second transistor between said second and third nodes and a fourth node and responsive to said potential difference for maintaining said potential difference between said second node and said third node;

wherein said constant current source comprises;

a fifth transistor and a sixth transistor responsive to said clock signal and a complimentary clock signal so as to provide a second major current path from one of said first and fourth nodes; and

wherein said clock controller comprises;

a first logic circuit connected between said fourth node and a second source of power voltage for performing a first logic function in response to said clock data signal, and

a second logic circuit connected between said fifth transistor and said second source of power voltage for performing a second logic function which is inverse to said first logic function in response to a complementary clock data signal.

2. The flip flop circuit as set forth in claim 1, in which each of said first transistor to said sixth transistor is a field effect transistor.

3. The flip flop circuit as set forth in claim 1, in which said first logic circuit and said second logic circuit are implemented by an OR gate and an AND gate, respectively.

4. The flip flop circuit as set forth in claim 1, in which said data storage circuit and said clock controller serve as a master section forming in combination a master-slave flip flop circuit together with a slave section.

5. The flip flop circuit as set forth in claim 4, in which said slave section comprises

a second data storage circuit, and

a second clock controller.

6. The flip flop circuit as set forth in claim 5, wherein:

said second data storage circuit comprises;

a third resistor connected to said first source of power voltage,

a fourth resistor connected to said first source of power voltage.

7. The flip flop circuit as set forth in claim 6, in which each of said first transistor to said twelfth transistor is a field effect transistor.

8. The flip flop circuit as set forth in claim 6, wherein said first and third logic circuits each comprise an OR gate and said second and fourth logic circuits each comprise an AND gate.

9. A frequency divider comprising

a first delayed flip flop circuit responsive to a clock signal for producing a first output signal twice longer in pulse repetition period than said clock signal and a first complementary output signal complementary to said first output signal,

a plurality of second delayed flip flop circuits connected in cascade, each of said plurality of second delayed flip flop circuit comprising:

a data storage circuit comprising;

a differential amplification stage connected to a first source of power voltage level and having a data input node supplied with a second complementary output signal complementary to a second output signal and a pair of output data nodes for producing said second output signal and said second complementary output signal and

a constant current source connected to said differential amplification stage and responsive to said clock signal so as to enable said differential amplification stage, and

a clock controller connected to said constant current source for controlling said constant current source in accordance with said first complementary output signal, said clock signal.

10. The frequency divider as set forth in claim 9, wherein said clock controller comprises an OR gate.