Analog delay circuit

• US 5,945,863 A
• Filed: 06/18/1997
• Issued: 08/31/1999
• Est. Priority Date: 06/18/1997
• Status: Expired due to Term

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Coy, Bruce H.
• Primary Examiner(s): Callahan, Tim
• Assistant Examiner(s): Shin, Eunja
• Application Number:
  US08/878,162
• Time in Patent Office: 804 Days
• Field of Search: 327/231, 327/232, 327/246, 327/247, 327/269-272, 327/252, 327/253, 327/266, 327/270, 327/274, 327/276-278, 327/280, 327/284, 327/285, 327/287
• US Class Current: 327/280
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.

Claims

1. A delay circuit, comprising:

a first differential pair of emitter-coupled transistors with a first adjustable delay;

at least a second differential pair of emitter-coupled transistors with a second adjustable delay;

the first and second differential pairs of emitter-coupled transistors being connected to a common input and a common output to provide a composite adjustable delay between the common input and common output that combines the first and second adjustable delays;

a register for containing a digital code;

a current digital-to-analog converter (DAC) connected to the register for providing a pair of complementary currents in response to the digital code, the current DAC being connected to provide a first current of the pair of complementary currents to the first differential pair and to provide a second current of the pair of complementary currents to the second differential pair; and

,

wherein the first and second differential pairs each include first and second emitter-coupled transistors, the delay circuit further including a first resistor connected to the base of a first transistor of the second differential pair and a second resistor connected to the base of a second transistor of the second differential pair.

2. The delay circuit of claim 1, further including means connected to the register for providing the digital code.

3. The delay circuit of claim 2, wherein the means includes a data bus.

4. An integrated circuit with one or more electronic circuits, in which at least one of the electronic circuits includes an analog delay circuit having:

a first differential pair of emitter-coupled transistors with a first adjustable delay;

at least a second differential pair of emitter-coupled transistors with a second adjustable delay;

the first and second differential pairs of emitter-coupled transistors being connected to a common input and a common output to provide a composite adjustable delay between the common input and common output that combines the first and second adjustable delays;

a register for containing a digital code;

a current digital-to-analog converter (DAC) connected to the register for providing a pair of complementary currents in response to the digital code, the current DAC being connected to provide a first current of the pair of complementary currents to the first differential pair and to provide a second current of the pair of complementary currents to the second differential pair; and

,

wherein the first and second differential pairs each include first and second emitter-coupled transistors, the delay circuit further including a first resistor connected to the base of a first transistor of the second differential pair and a second resistor connected to the base of a second transistor of the second differential pair.

5. The integrated circuit of claim 4, wherein the analog delay circuit further includes means connected to the register for providing the digital code.

6. The integrated circuit of claim 5, wherein the means includes a data bus.

7. A delay circuit comprising:

a plurality of cascaded delay stages, each delay stage including a common input and a common output, and;

a first differential pair of emitter-coupled transistors with a first adjustable delay;

at least a second differential pair of emitter-coupled transistors with a second adjustable delay; and

the first and second differential pairs of emitter-coupled transistors being connected to the common input and the common output to provide a composite adjustable delay between the common input and common output that combines the first and second adjustable delays;

a register for containing a digital code;

a current digital-to-analog converter (DAC) connected to the register for providing a pair of complementary currents in response to the digital code, the current DAC being connected to provide a first current of the pair of complementary currents to the first differential pair of each delay stage and to provide a second current of the pair of complementary currents to the second differential pair of each delay stage; and

,

wherein, for said each delay stage, the first and second differential pairs each include first and second emitter-coupled transistors, said each delay stage further including a first resistor connected to the base of a first transistor of the second differential pair and a second resistor connected to the base of a second transistor of the second differential pair.

8. The delay circuit of claim 7, further including means connected to the register for providing the digital code.

9. The delay circuit of claim 8, wherein the means includes a data bus.

10. An integrated circuit with one or more electronic circuits, at least one electronic circuit including the delay circuit of claim 7.

11. The integrated circuit of claim 10, wherein the delay circuit includes semiconductor devices selected from the group including IFET, MOSFET, BIPOLAR, and GaSaFET devices.