Enhanced function board for use in processing image data and image processing apparatus using the same

• US 5,946,004 A
• Filed: 02/10/1997
• Issued: 08/31/1999
• Est. Priority Date: 02/19/1996
• Status: Expired due to Fees

• Current Assignee: Sega Enterprises LTD.
• Original Assignee: Sega Enterprises LTD.
• Inventors: Suzuki, Masayuki, Kuroda, Ryoji, Kitamura, Kenya, Morioka, Seisuke
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Luu, Sy D.
• Application Number:
  US08/796,476
• Time in Patent Office: 932 Days
• Field of Search: 345/502, 345/503, 345/202, 463/31
• US Class Current: 345/502
• CPC Class Codes: A63F 13/23 for interfacing with the game device, e.g. specific interfaces between game controller and console
• CPC Class Codes: A63F 13/52 involving aspects of the displayed game scene
• CPC Class Codes: A63F 13/95 Storage media specially adapted for storing game information, e.g. video game cartridges
• CPC Class Codes: A63F 2300/1025 details of the interface with the game device, e.g. USB version detection
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: A63F 2300/66 for rendering three dimensional images
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence

Abstract

A video game device is disclosed which is composed of a console apparatus in which a processor is installed to execute a game software program. The video game device also includes a memory device, such as a memory cartridge which is removably attached to the console apparatus and which stores the game program. An enhanced function board is attached to the main body of the video game device for improving and enhancing the functions of the video game. The enhanced function board includes a pair of buses, first and second digital processors connected to the buses, a FIFO memory connected between the buses, and an interface circuit connected to the pair of buses. The interface circuit operates to connect the first and second digital processors to the processor of the video game device.

Claims

1. An enhanced function board, which can be connected via a connector to an image processing apparatus that includes a CPU, a memory in which image data is stored, and a video signal processor for accessing said memory to read said image data and prepare a display image based on said image data under control of said CPU, the enhanced function board comprising:

a pair of buses;

first and second digital signal processors respectively connected to said pair of buses;

a FIFO memory connected between said pair of buses for transferring data between said first and second digital signal processors; and

an interface circuit connected to said pair of buses, whereby said first and said second digital signal processors are connected via said interface circuit to said CPU and said video signal processor.

2. The enhanced function board according to claim 1, wherein said image processing apparatus comprises;

a first bus connected to said memory in which image data is stored, and

a second bus connected to said video signal processor, and

said interface circuit connects said first and second buses to said pair of buses to which said first and second digital signal processors are connected.

3. The enhanced function board according to claim 2, wherein said memory in which said image data is stored is a ROM(Read Only Memory) that is retained in a memory cartridge that is removably attached to said image processing apparatus.

4. The enhanced function board according to claim 3, wherein said image processing apparatus further comprises a third bus connected to said CPU, and a main board mounted with a first connector to which said memory cartridge is removably attached, and second through fourth connectors respectively connected to said first through third buses, and a fifth connector connected at least to a timing signal line;

and

wherein, from among said first through fifth connectors mounted on said main board, a first set of connectors that engage said second through fifth connectors are provided on one surface at locations corresponding to those of said second through fifth connectors mounted on said main board.

5. The enhanced function board according to claim 4, further comprising a second set of connectors mounted at positions, on the other surface opposite to said one surface, corresponding to said first set of connectors.

6. An image processing apparatus comprising:

a main body including a CPU, a memory device in which image data is stored, and a video signal processor for accessing said memory to read said image data and for preparing display data based on said image data under the control of said CPU; and

an enhanced function board, connected via a connector to said main body, and including a pair of buses, first and second digital signal processors connected to said pair of buses respectively, a FIFO memory connected between said pair of buses for operatively connecting said first and second digital signal processors to said CPU and said video signal processor.

7. The enhanced function board according to claim 6, wherein said enhanced function board further comprise a first bus connected to said memory device and a second bus connected to said video signal processor, and wherein said interface circuit connects said first and second buses to said first and said second digital signal processors, respectively.

8. The image processing apparatus according to claim 6, wherein said memory device is a Read Only Memory retained in a memory cartridge removably attached to said main body for storing a game program, which is executed by the said CPU.

9. The image processing apparatus according to claim 6, wherein said image data include data for a background image and for an object image displayed on said background image, and wherein said video signal processor includes a first processor for performing a deformation process on said object image, and a second processor for controlling scrolling of said background image.

10. The image processing apparatus according to claim 9, wherein said CPU, said first digital signal processor, said FIFO memory and said second digital signal processor are connected in series by said interface circuit of said enhanced function board, and wherein said first processor and second processor are connected in parallel to said second digital signal processor.

11. The image processing apparatus according to claim 9, wherein said first and second digital signal processors are connected in parallel to said CPU by said interface circuit of said enhanced function board, and wherein said first and second processors are respectively connected in parallel to said first and second digital signal processors.

12. The image processing apparatus according to claim 9, wherein said first and second digital signal processors are connected in parallel to said CPU by said interface circuit of said enhanced function board, and wherein said first and second processors are connected in parallel to said first or second digital signal processor.

13. The image processing apparatus according to claim 9, wherein said first digital signal processor receives three-dimensional coordinate image data from said CPU and transforms said three-dimensional coordinate image data into corresponding two-dimensional coordinate image data, and said enhanced function board further includes a circuit for receiving a specific address from said CPU, and for performing a comparison to detect a data position corresponding to said specific address for said transformed two-dimensional coordinate image data.

14. The image processing apparatus according to claim 6, wherein said first digital signal processor receives three-dimensional coordinate image data from said CPU and transforms said three-dimensional coordinate image data into corresponding two-dimensional coordinate image data, and said enhanced function board further includes a circuit for receiving a specific address from said CPU, and for performing a comparison to detect a data position corresponding to said specific address for said transformed two-dimensional coordinate image data.