Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns

• US 5,946,214 A
• Filed: 07/11/1997
• Issued: 08/31/1999
• Est. Priority Date: 07/11/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Wen, Ping, Heavlin, William D., Kittler, Richard C.
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): THOMAS, CAROLYN D
• Application Number:
  US08/891,586
• Time in Patent Office: 781 Days
• Field of Search: 364/468.28, 364/468.17, 364/468.01, 364/468.02, 365/200, 365/201, 711/161, 711/162, 711/100, 711/120, 395/308, 395/309, 395/183.18, 395/182.04, 395/182.12, 395/183.19
• US Class Current: 700/121
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H10B 99/22 including field-effect components

Abstract

A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers λ of failures for the failure modes respectively. The numbers λ are optimized by minimizing a least squares difference between the observed repair rates and the model repair rates. The fabrication yield is computed as a predetermined function of the model repair rate including scale factor(s) for the circuit on the wafer being designed. The method can be used to select a redundancy scheme for the wafer by computing fabrication yields for a plurality of candidate redundancy schemes, and selecting the redundancy scheme which has the highest return for additional test, manufacturing and design investment.

Claims

1. A computer implemented method for estimating a fabrication yield for a semiconductor product under design including a plurality of design integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme, comprising the steps of:

(a) performing a bitmap failure analysis of an existing semiconductor product including a plurality of existing integrated circuit dies having bitmap failure modes that are comparable to those of the design dies to obtain a number of failed caches;

(b) calculating an observed repair rate as a ratio of a number of said failed caches that can be repaired by the predetermined redundancy scheme to a total of said number of failed caches;

(c) computing, using a computer, a model repair rate for the predetermined redundancy scheme which approximates the observed repair rate using a discrete multivariate probability distribution model including computed average numbers λ

of failures for the failure modes respectively; and

(d) calculating the fabrication yield as a predetermined function of the model repair rate including a scale factor for the semiconductor product under design.

2. A method as in claim 1, in which the model is based on a plurality of discrete probability models.

3. A method as in claim 1, in which step (c) comprises optimizing the model using a minimum least squares difference between the observed repair rate and the model repair rate.

4. A method as in claim 1, further comprising using a computer to perform the steps, prior to step (c), of:

(e) using the model to calculate model repair rates as ratios of numbers of said failed caches that can be repaired by a plurality of redundancy schemes to a total of said number of failed caches for at least as many redundancy schemes as failure modes respectively; and

(f) optimizing the numbers λ

such that the model repair rates most closely approximate the observed repair rates respectively.

5. A method as in claim 4, in which step (f) comprises minimizing a least squares difference between the observed repair rates and the model repair rates.

6. A method as in claim 4, in which the model is based on a plurality of discrete multivariate probability models.

7. A method as in claim 6, in which the plurality of discrete multivariate probability models are represented by a multiple Poisson model having the form:

##EQU5## where m is a number of the failure modes, j is an index for the failure modes, X_j is a random variable for the failure modes j, k_j is a number of failures, and Pr is the probability of occurrence of k_j failures of failure mode j.

8. A method as in claim 4, in which the model repair rate for a redundancy scheme RxCy has the form:

##EQU6## where i is an index for failure modes, k_i is the number of failures of failure mode i, X_i is a random variable for the number of failure for modes i, and Pr is the probability of occurrence of k_i failures of failure mode i over all the failure modes i.

9. A method as in claim 1, in which the scale factor includes a ratio of a cache area to a die area.

10. A method as in claim 9, in which the predetermined function has the form:

space="preserve" listing-type="equation">Y'"'"'=Y+Y.sup.(1-α

) ×

(1-Y.sup.α

)×

R

where Y'"'"' is the fabrication yield, Y is a yield without requiring repair by the redundancy scheme, α

is the ratio of the cache area to the die area, and R is the model repair rate.

11. A method as in claim 9, in which the predetermined function has the form:

space="preserve" listing-type="equation">Y'"'"'=Y+Y.sup.(1-α

) ×

(1-Y.sup.α

)×

R

where Y'"'"' is the fabrication yield, Y is a yield without requiring repair by the redundancy scheme, α

is the ratio of the cache area to the die area multiplied by a sensitivity factor, and R is the model repair rate.

12. A method as in claim 1, in which the predetermined function has the form:

space="preserve" listing-type="equation">Y'"'"'=Y+Y.sup.(1-α

) ×

(1-Y.sup.α

)×

R

where Y'"'"' is the fabrication yield, Y is a yield without requiring repair by the redundancy scheme, α

is sensitivity factor which is calculated by solving the predetermined function for α

using empirically determined values of Y, Y'"'"' and R for an existing semiconductor product, and R is the model repair rate.

13. A method as in claim 1, in which:

the cache comprises a plurality of sections; and

the predetermined function comprises a scale factor for each section respectively.

14. A method as in claim 13, in which the predetermined function has the form:

##EQU7## where Y'"'"' is the fabrication yield, Y is a yield without requiring repair by the redundancy scheme, n is a number of the sections, i is an index for the sections, α

_i is the ratio of an area of the section i to the cache area and constitutes said scale factor, and R_i is the model repair rate for the section i.

15. A method as in claim 1, in which the scale factor is a predetermined function of a number of rows and/or columns in the cache of each design die and a number of rows in the cache of each existing die.

16. A method as in claim 15, in which the scale factor is substantially equal to the number of rows and/or columns in the cache of each design die to the number of rows in the cache of each existing die.

17. A method as in claim 1, in which:

each design die further includes a logic section; and

the scale factor is a predetermined function of an area of the cache and an area of the logic section.

18. A method as in claim 17, in which the scale factor is substantially equal to a ratio of the area of the cache to the sum of the areas of the cache and the logic section.

19. A method as in claim 1, further comprising the steps of:

(e) repeating steps (b) to (d) for a plurality of predetermined redundancy schemes from which said predetermined redundancy scheme can be selected; and

(f) selecting said predetermined redundancy scheme as the one of said plurality of predetermined redundancy schemes for which a cost factor is lowest.

20. A computer implemented method for creating a fabrication yield model for a semiconductor product under design including a plurality of design integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme, comprising the steps of:

(a) performing a bitmap failure analysis of an existing semiconductor product including a plurality of existing integrated circuit dies having bitmap failure modes that are comparable to those of the design dies to obtain a number of failed caches;

(b) calculating an observed repair rate as a ratio of a number of said failed caches that can be repaired by the predetermined redundancy scheme to a total of said number of failed caches;

(c) creating a multivariate probability distribution model on a computer including average numbers λ

of failures for the failure modes respectively;

(d) calculating, using the model on the computer, model repair rates as ratios of numbers of said failed caches that can be repaired by a plurality of redundancy schemes to a total of said number of failed caches for at least as many redundancy schemes as failure modes respectively; and

(d) optimizing the numbers λ

using a computer such that the model repair rates most closely approximate the observed repair rates respectively by minimizing a least squares difference between the observed repair rates and the model repair rates.

21. A method as in claim 20, in which the model is based on a multiple Poisson model.

22. A method as in claim 20, in which the multiple Poisson model has the form:

##EQU8## where m is a number of the failure modes, j is an index for the failure modes, X_j is a random variable for the failure modes j, k_j is a number of failures, and Pr is the probability of ccurrence of k_j failures of failure mode j.

23. A method as in claim 20, in which the model repair rate for a redundancy scheme RxCy has the form:

##EQU9## where i is an index for failure modes, k_i is the number of failures of failure mode i, X_i is a random variable for the number of failure for modes i, and Pr is the probability of occurrence of k_i failures of failure mode i over all the failure modes i.