×

Computer implemented method for estimating fabrication yield for semiconductor integrated circuit including memory blocks with redundant rows and/or columns

  • US 5,946,214 A
  • Filed: 07/11/1997
  • Issued: 08/31/1999
  • Est. Priority Date: 07/11/1997
  • Status: Expired due to Fees
First Claim
Patent Images

1. A computer implemented method for estimating a fabrication yield for a semiconductor product under design including a plurality of design integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme, comprising the steps of:

  • (a) performing a bitmap failure analysis of an existing semiconductor product including a plurality of existing integrated circuit dies having bitmap failure modes that are comparable to those of the design dies to obtain a number of failed caches;

    (b) calculating an observed repair rate as a ratio of a number of said failed caches that can be repaired by the predetermined redundancy scheme to a total of said number of failed caches;

    (c) computing, using a computer, a model repair rate for the predetermined redundancy scheme which approximates the observed repair rate using a discrete multivariate probability distribution model including computed average numbers λ

    of failures for the failure modes respectively; and

    (d) calculating the fabrication yield as a predetermined function of the model repair rate including a scale factor for the semiconductor product under design.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×