Continuous burst EDO memory device

• US 5,946,265 A
• Filed: 07/11/1997
• Issued: 08/31/1999
• Est. Priority Date: 12/14/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/891,557
• Time in Patent Office: 781 Days
• Field of Search: 365/189.05, 365/230.08, 365/233, 365/236, 365/238.5
• US Class Current: 365/230.01
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latch a memory address from external address lines and internally generates additional memory addresses. The integrated circuit memory can output data in a continuous stream while new rows of the memory are accessed. A method and circuit are described for outputting a burst of data stored in a first row of the memory while accessing a second row of the memory.

Claims

1. A synchronous memory device comprising:

an input for receiving a clock signal;

a plurality of addressable memory elements;

a plurality of external address inputs;

address counter circuitry for receiving a first address on the plurality of external address inputs, and for generating a sequence of addresses in response to the first address and the clock signal; and

output buffer circuitry adapted to drive a sequence of data from the memory device, the output buffer circuitry further adapted to continue to drive the sequence of data from the memory device while a new address is received by the address counter circuity.

2. The synchronous memory device of claim 1 wherein the address counter circuitry comprises:

an address latch circuit coupled to the plurality of external address inputs; and

a counter coupled to the address latch circuit for generating the sequence of addresses.

3. The synchronous memory device of claim 1 further comprising:

access circuitry for reading data stored in the plurality of addressable memory elements.

4. The synchronous memory device of claim 1 further comprising:

a write enable signal input for receiving an enable signal; and

termination circuitry coupled to the output buffer circuitry for terminating an output of the sequence of data.

5. A synchronous memory device comprising:

an input for receiving a clock signal;

a plurality of addressable memory elements arranged in rows and columns;

a plurality of external address inputs;

address circuitry for receiving row addresses and column addresses from the plurality of external address inputs;

counter circuitry for generating a sequence of column addresses in response to a first received clock signal;

row access circuitry for accessing a row of memory elements in response to a received first row address;

output buffer circuitry adapted to output a sequence of data from the memory device, the sequence of data being stored in the plurality of addressable memory elements having addresses corresponding to the sequence of addresses and the first row address; and

control circuitry for controlling the output buffer circuitry and the access circuitry, wherein a second row of memory elements can be accessed without interrupting an active output sequence of data from the first row address.

6. The memory device of claim 5 further comprising:

a write enable signal input for receiving an enable signal; and

termination circuitry coupled to the output buffer circuitry for terminating an output of the sequence of data.

7. A memory device comprising:

a plurality of addressable memory elements;

a plurality of external address inputs;

first means for receiving a first address on the plurality of external address inputs, and for generating a sequence of addresses in response to the first address; and

second means for driving a sequence of data from the memory device while a new address is received by the first means.

8. The memory device of claim 7 wherein the memory device is a dynamic random access memory.

9. The memory device of claim 7 wherein the memory device is a synchronous dynamic random access memory.

10. A method of reading data from a synchronous memory device having a plurality of addressable memory elements arranged in rows and columns, the method comprising the steps of:

receiving a first row address;

receiving a first column address;

accessing a row of memory elements having the first row address;

generating a sequence of column addresses starting at the first column address;

outputting data stored at the sequence of column addresses;

receiving a second row address while outputting the data stored at the sequence of column addresses; and

accessing a row of memory elements having the second row address while outputting the data stored at the sequence of column addresses.

11. The method of claim 10 further including the step of:

initializing a burst read operation on an edge of the clock signal.

12. The method of claim 10 further including the steps of:

receiving a signal on a write enable input; and

terminating the step of outputting data in response to the signal on the write enable input.

13. The method of claim 10 further including the steps of:

initializing a burst write operation on an edge of the clock signal;

receiving a second column address;

generating a second sequence of column addresses starting at the second column address; and

storing data in a plurality of addressable memory elements having address corresponding to the second sequence of column addresses.

14. The method of claim 10 further including the steps of:

receiving a second column address;

accessing a row of memory elements having the second row address;

generating a second sequence of column addresses starting at the second column address; and

outputting data stored at the second sequence of column addresses.

15. The method of claim 10 wherein the sequence of data is output in response to the clock signal.