System and method for ensuring integrity of audio

• US 5,946,396 A
• Filed: 10/25/1996
• Issued: 08/31/1999
• Est. Priority Date: 10/25/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Davis, Derek L.
• Primary Examiner(s): Gregory, Bernarr E.
• Application Number:
  US08/738,086
• Time in Patent Office: 1,040 Days
• Field of Search: 380/5, 380/10, 380/23, 380/25, 380/4, 380/9, 380/49, 380/50, 380/59, 380/19, 380/30, 348/460, 348/552
• US Class Current: 713/178
• CPC Class Codes: H04L 2209/60 Digital content management, e.g. content distribution
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/3236 using cryptographic hash functions
• CPC Class Codes: H04L 9/3297 involving time stamps, e.g. generation of time stamps

Abstract

Implemented preferably within a video camera, a cryptographic device is used to prevent audio from being fraudulently altered without detection. The cryptographic device performs a "time-bracketing" operation to preserve data integrity through implementation of a state value randomly generated after a first point of time. Time-bracketing is performed by appending the state value to an aggregate digest of at least one pair of video and audio data clips to produce an aggregate data set, and digitally signing the aggregate data set before the aggregate digest is transmitted to a centralized system for "time-stamping", resulting in a published composite digest. The aggregate data set supports that the data clips were captured after the first point of time while providing support that the data clip was captured before the second point of time.

Claims

1. A system for determining whether a plurality of data clips, including a video data clip and a corresponding audio data clip, are captured between a first point of time and a second point of time, the system comprising:

a first electronic device including logic to produce an aggregate data set by digitally signing (i) a periodically changing state value available at the first point of time, and an aggregate digest being a result formed by hash and arithmetic operations on the plurality of data clips; and

a centralized system in communication with the first electronic device, the centralized system to receive the aggregate digest from the first electronic device, and to produce a composite digest at the second period of time.

2. The system according to claim 1, wherein the first electronic device further including logic to store the aggregate data set, the plurality of data clips and the state value.

3. The system according to claim 1 further including a second electronic device coupled to the first electronic device, said second electronic device including logic to store the aggregate data set, the plurality of data clips and the state value.

4. The system according to claim 1, wherein the first electronic device to perform verification that the plurality of data clips were captured between the first point of time and the second point of time by analyzing and comparing the contents of the composite digest and the aggregate data set.

5. The system according to claim 1, wherein the logic of the first electronic device includes:

a sensor to capture the plurality of data clips; and

a cryptographic circuit coupled to the sensor, the cryptographic circuit including

an internal bus,

a first storage element coupled to the internal bus, the first storage element being loaded with the state value prior to the sensor beginning to capture the plurality of data clips, and

a processing unit coupled to the internal bus.

6. The system according to claim 5, wherein the cryptographic circuit further includes a non-volatile memory element coupled to the internal bus, said non-volatile memory element to contain a unique public key and a unique private key associated with the unique public key.

7. The system according to claim 5, wherein the cryptographic circuit further includes a random number generator coupled to the internal bus.

8. The system according to claim 5, wherein the processing unit of the cryptographic circuit to (i) receive the plurality of data clips from the sensor, (ii) produce a plurality of digests associated with the plurality of data clips, (iii) perform hash operations on each of the plurality of digests and combine results of the hash operations to produce the aggregate digest, and (iv) digitally sign the state value and the aggregate digest to produce the aggregate data set.

9. The system according to claim 5, wherein the cryptographic circuit further includes a volatile memory element to contain at least the aggregate digest.

10. The system according to claim 5, wherein the sensor includes a pixel capture array and control logic controlling the pixel capture array.

11. The system according to claim 10, wherein the sensor further includes an analog-to-digital converter.

12. The system according to claim 1, wherein the aggregate data set includes an encrypted format of the state value concatenated to the aggregate digest.

13. The system according to claim 1, wherein the aggregate data set includes an encrypted format of the state value interwoven with data associated with the aggregate digest.

14. The system according to claim 1, wherein the logic performing the hash and arithmetic operations comprises (i) logic to concatenate each of the plurality of data clips, and (ii) logic to perform the hash operation on a concatenated version of the plurality of data clips to produce the aggregate digest.

15. The system according to claim 1, wherein the logic performing the hash and arithmetic operations comprises (i) logic to interleave data associated with each of the plurality of data clips to produce a sequence of data, and (ii) logic to perform the hash operation on the sequence of data to produce the aggregate digest.

16. The system according to claim 1, wherein the periodicity in changing the state value is random by nature.

17. The system according to claim 16, wherein the state value remains static once one of the plurality of data clips begins to be captured by the first electronic device.

18. The system according to claim 17, wherein the state value is changed before a next plurality of data clips are captured.

19. A system ensuring integrity of a plurality of data clips, including a video data clip and a corresponding audio data clip, to be captured between a first point of time and a second point of time, the system comprising:

electronic means for processing the data clips, said electronic means including

sensing means for capturing the plurality of data clips after the first point of time, and

cryptographic means for performing hash and arithmetic operations on the plurality of data clips to produce an aggregate digest, for combining the aggregate digest with a periodically changing state value loaded into the electronic means at the first period of time, for digitally signing the state value and the aggregate digest to produce an aggregate data set, and for storing at least the aggregate data set; and

centralized means for receiving the aggregate digest from the electronic device, and for producing a composite digest at the second period of time, said centralized means being in communication with the electronic means.

20. The system according to claim 19, wherein the cryptographic means includes logic to perform a hash operation on each of the plurality of data clips to produce a plurality of hash results, and logic to concatenate each of the plurality of hash results to produce the aggregate digest.

21. A method for preserving integrity of audio by ensuring that the audio has been captured after a first point of time and before a second point of time, the method comprising:

combining a periodically changing state value with an aggregate digest;

digitally signing the aggregate digest and the state value to produce an aggregate data set; and

outputting the aggregate digest to be incorporated within a composite digest published at the second point of time.

22. The method according to claim 21, wherein the state value is unique.

23. The method according to claim 21, wherein the act of combining includes appending the state value to the aggregate digest.

24. The method according to claim 21, wherein the act of combining includes interleaving the state value with the aggregate digest.

25. The method of claim 21, wherein prior to the combining the state value with the aggregate digest, the method further comprising:

loading the state value created at the first period of time within a first storage element the electronic device;

capturing the plurality of data clips by the electronic system; and

producing the aggregate digest from the plurality of data clips.

26. The method according to claim 25, wherein the act of producing the aggregate digest includes:

producing an aggregate data clip by performing hash and arithmetic operations on the plurality of data clips; and

producing an aggregate digest by performing hash operations on the aggregate data clip.

27. An electronic device comprising:

circuitry to perform operations on a plurality of data clips to form an aggregate digest; and

circuitry to digitally sign a periodically changing state value, available at the first point of time, in combination with the aggregate digest.

28. The electronic device according to claim 27, further comprising circuitry to capture the plurality of data clips.

29. The electronic device according to claim 28, wherein the capture circuitry comprises a sensor including a pixel capture array and control logic controlling the pixel capture array.

30. The electronic device according to claim 28, wherein the capture circuitry comprises a sensor including an analog-to-digital converter.

31. The electronic device according to claim 27, wherein the plurality of data clips include a video data clip and an audio data clip.

32. The electronic device according to claim 27, wherein the periodicity in changing of the state value is random by nature.

33. The electronic device according to claim 27, wherein the operations include hash operations.

34. The electronic device according to claim 33, wherein the operations include arithmetic operations.

35. The electronic device according to claim 27, wherein the digital signing circuitry includes:

an internal bus;

a first storage element coupled to the internal bus, the first storage element being loaded with the state value prior to capturing the plurality of data clips; and

a processing unit coupled to the internal bus.

36. The electronic device according to claim 35, the digital signing circuitry further comprising a non-volatile memory element coupled to the internal bus, said non-volatile memory element to contain a unique public key and a unique private key associated with the unique public key.

37. The electronic device according to claim 36, wherein the digital signing circuitry further comprises a random number generator coupled to the internal bus.

38. The electronic device according to claim 35, wherein the processing unit of the digital signing circuitry further produces a plurality of digests associated with the plurality of data clips and performs hash operations on each of the plurality of digests and combine results of the hash operations to produce the aggregate digest.

39. The electronic device according to claim 35, wherein the cryptographic circuit further includes a volatile memory element to contain at least the aggregate digest.