Method for generating a secure macro element of a design for a programmable IC

• US 5,946,478 A
• Filed: 05/16/1997
• Issued: 08/31/1999
• Est. Priority Date: 05/16/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lawman, Gary R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US08/857,439
• Time in Patent Office: 837 Days
• Field of Search: 364/488-491, 395/500.02-500.19, 326/68, 326/39
• US Class Current: 716/117
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of generating and using a secure macro element for configuring programmable ICs is provided. The method provides a bitstream to a user, rather than providing a user-editable macro. Compilation software is provided to the user that combines the data from a "macro bitstream" (the bitstream comprising the macro data description) and the data from the user'"'"'s own circuits to create the complete bitstream. The compilation software reserves the relevant portions of the complete bitstream for the macro, and does not assign user circuits to the areas controlled by those portions of the bitstream. In one embodiment of the invention, the user specifies a physical location on the programmable IC for the macro, so the macro data is optionally placed in a different location in the complete bitstream than in the macro bitstream. In another embodiment, the macro bitstream and the complete bitstream represent the same programmable IC architecture, but not the same device, so they are of similar formats but different lengths.

Claims

1. A method for including a macro in a programmable IC, comprising the steps of:

a) generating a macro bitstream;

b) providing said macro bitstream to a user;

c) generating a user circuit description; and

d) combining said macro bitstream and said user circuit description to generate a complete bitstream for programming the programmable IC.

2. The method of claim 1, wherein the programmable IC is an FPGA.

3. The method of claim 1, wherein said user circuit description comprises a netlist.

4. The method of claim 1, wherein the macro has predictable timing.

5. The method of claim 1, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

said complete bitstream data is different from said macro bitstream data, said complete bitstream data having been altered from said macro bitstream data to permit connections between signals in the macro and circuits in said user circuit description.

6. The method of claim 1, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

said complete bitstream data is different from said macro bitstream data, said complete bitstream data having been altered from said macro bitstream data to permit the addition of user logic to the area of the programmable IC encompassed by the macro.

7. The method of claim 1, where said macro bitstream and said complete bitstream are of different lengths.

8. The method of claim 1, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

the position of said macro bitstream data within said macro bitstream is different from the position of said complete bitstream data within said complete bitstream.

9. The method of claim 1, further comprising the step of:

generating a macro placeholder to be used in generating said user circuit description.

10. The method of claim 9, further comprising the step of:

modifying said macro placeholder to specify the location of the macro in the programmable IC.

11. The method of claim 9, further comprising the step of:

providing said macro placeholder to the user.

12. A method for using a macro for a programmable IC, comprising the steps of:

a) generating a user circuit description for a user design;

b) receiving a macro bitstream;

c) specifying that the macro be included in the user design; and

d) producing a complete bitstream for a programmable IC by combining said circuit description and said macro bitstream.

13. The method of claim 12, wherein the programmable IC is an FPGA.

14. The method of claim 12, wherein said user circuit description comprises a netlist.

15. The method of claim 12, wherein the macro includes routing, thereby providing predictable timing.

16. The method of claim 12, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

said complete bitstream data is different from said macro bitstream data, said complete bitstream data having been altered from said macro bitstream data to permit connections between signals in the macro and circuits in said user circuit description.

17. The method of claim 12, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

said complete bitstream data is different from said macro bitstream data, said complete bitstream data having been altered from said macro bitstream data to permit the addition of user logic to the area of the programmable IC encompassed by the macro.

18. The method of claim 12, where said macro bitstream and said complete bitstream are of different lengths.

19. The method of claim 12, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

the position of said macro bitstream data within said macro bitstream is different from the position of said complete bitstream data within said complete bitstream.

20. The method of claim 12, further comprising the step of:

receiving a macro placeholder to be used in specifying that the macro be included in the user design.

21. The method of claim 20, further comprising the step of:

modifying said macro placeholder to specify the location of the macro in the programmable IC.

22. The method of claim 12, further comprising the step of:

setting software parameters to reserve for the macro both an area of the programmable IC and the related portion of said complete bitstream.

23. The method of claim 12, further comprising the step of:

setting software parameters to specify the location of the macro in the programmable IC.

24. The method of claim 12, wherein said macro bitstream is encrypted.

25. A method for generating a macro bitstream for inclusion in a complete bitstream for programming a programmable IC, comprising the steps of:

a) creating bitstream data representing a macro;

b) placing said bitstream data representing said macro into one or more portions of a macro bitstream; and

c) completing said macro bitstream by filling the remaining portions of said macro bitstream with data at least some of which will be omitted from the complete bitstream.

26. The method of claim 25, wherein the programmable IC is an FPGA.

27. The method of claim 25, wherein said macro includes routing, thereby providing predictable timing.

28. The method of claim 25, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

said complete bitstream data is different from said macro bitstream data.

29. The method of claim 28, wherein:

said complete bitstream data is altered from said macro bitstream data to permit connections between signals in the macro and circuits in said user circuit description.

30. The method of claim 28, wherein:

said complete bitstream data is altered from said macro bitstream data to permit the addition of user logic to the area of the programmable IC encompassed by the macro.

31. The method of claim 25, where said macro bitstream and said complete bitstream are of different lengths.

32. The method of claim 25, wherein:

one or more portions of said macro bitstream comprise macro bitstream data representing the macro;

one or more portions of said complete bitstream comprise complete bitstream data representing the macro; and

the position of said macro bitstream data within said macro bitstream is different from the position of said complete bitstream data within said complete bitstream.

33. The method of claim 25, wherein:

said data at least some of which will be omitted from the complete bitstream comprises data bits that make it difficult to isolate the macro data from the macro bitstream.

34. The method of claim 25, further comprising the step of:

d) providing said completed macro bitstream to a user.

35. The method of claim 25, further comprising the step of:

d) encrypting said completed macro bitstream.

36. The method of claim 35, further comprising the step of:

e) providing said encrypted macro bitstream to a user.

37. A method for providing macro data for inclusion in a complete bitstream for programming a programmable IC, comprising the steps of:

a) creating bitstream data representing a macro;

b) placing said bitstream data representing said macro into one or more portions of a macro bitstream;

c) generating a macro placeholder to reserve for the macro both an area of the programmable IC and the related portion of the complete bitstream; and

d) providing said macro bitstream and said macro placeholder to a user.

38. A method for including a macro in a programmable IC, comprising the steps of:

a) generating a macro bitstream;

b) encrypting said macro bitstream;

c) providing said encrypted macro bitstream to a user;

d) generating a user circuit description; and

e) combining said encrypted macro bitstream and said user circuit description to generate a complete bitstream for programming the programmable IC.